參數(shù)資料
型號: AD7664AST
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit, 570 kSPS CMOS ADC
中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝: MS-026BBC, LQFP-48
文件頁數(shù): 5/19頁
文件大?。?/td> 392K
代理商: AD7664AST
REV. 0
AD7664
–5–
TO OUTPUT
PIN
1.6mA
I
OL
C
L
60pF
1
500 A
I
OH
1.4V
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C
L
= 10 pF
0.8V
t
DELAY
2V
2V
0.8V
0.8V
2V
t
DELAY
Figure 2. Voltage Reference Levels for Timing
PIN CONFIGURATION
48-Lead LQFP
(ST-48)
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
D
I
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12
AGND
AVDD
NC
DGND
OB/
2C
WARP
IMPULSE
SER/
PAR
NC = NO CONNECT
D0
D1
D2
D3
AD7664
D
D
D
O
O
D
D
D
D
D
D
N
N
N
N
N
N
N
N
N
I
R
R
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Type
Description
1
2
3, 40–48
4, 30
5
AGND
AVDD
NC
DGND
OB/
2C
P
P
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 5 V.
No Connect.
Must Be Tied to Analog Ground.
Straight Binary/Binary Two’s Complement. When OB/
2C
is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the
maximum throughput is achievable, and a minimum conversion rate must be applied in order
to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In
this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless
of the state of SER/
PAR
.
When SER/
PAR
is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/
INT
tied LOW, the internal
clock is selected on SCLK output. With EXT/
INT
set to a logic HIGH, output data is syn-
chronized to an external clock signal connected to the SCLK input.
When SER/
PAR
is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to select the active state
of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC is active
HIGH. When HIGH, SYNC is active LOW.
When SER/
PAR
is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to invert the SCLK sig-
nal. It is active in both master and slave mode.
DI
DI
6
WARP
DI
7
IMPULSE
DI
8
SER/
PAR
DI
9–12
DATA[0:3]
DO
13
DATA[4]
or EXT/
INT
DI/O
14
DATA[5]
or INVSYNC
DI/O
15
DATA[6]
or INVSCLK
DI/O
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