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| 型號： | AD7663ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT CMOS 5V 48LFCSP |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 41mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極 |
| 配用： | EVAL-AD7663CBZ-ND - BOARD EVALUATION FOR AD7663 |
REV. B
AD7663
–14–
75
70
65
60
55
50
45
40
35
0
10
100
1000
CMRR
–
dB
FREQUENCY – kHz
Figure 7. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the AD7663 behaves
like a one-pole RC filter consisting of the equivalent resistance of
the resistive scaler R/2 in series with R1 and CS. The resistor R1
is typically 2700
W and is a lumped component made up of some
serial resistors and the on-resistance of the switches. The capacitor
CS is typically 60 pF and is mainly the ADC sampling capacitor.
This one-pole filter with a typical –3 dB cutoff frequency of
800 kHz reduces undesirable aliasing effects and limits the noise
coming from the inputs.
Except when using the 0 V to 2.5 V analog input voltage range,
the AD7663 has to be driven by a very low impedance source to
avoid gain errors. That can be done by using a driver amplifier
whose choice is eased by the primarily resistive analog input
circuitry of the AD7663.
When using the 0 V to 2.5 V analog input voltage range, the input
impedance of the AD7663 is very high so the AD7663 can be
driven directly by a low impedance source without gain error.
That allows, as shown in Figure 5, putting an external one-pole
RC filter between the output of the amplifier output and the ADC
analog inputs to even further improve the noise filtering by the
AD7663 analog input circuit. However, the source impedance
has to be kept low because it affects the ac performances, especially
the total harmonic distortion (THD). The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD degradation is a function of the source impedance
and the maximum input frequency as shown in Figure 8.
FREQUENCY – kHz
–70
10
THD
100
1000
–80
–90
–100
–110
R = 100
R = 11
R = 50
Figure 8. THD vs. Analog Input Frequency and Input
Resistance (0 V to 2.5 V Only)
Driver Amplifier Choice
Although the AD7663 is easy to drive, the driver amplifier needs
to meet at least the following requirements:
The driver amplifier and the AD7663 analog input circuit
have to be able, together, to settle for a full-scale step of the
capacitor array at a 16-bit level (0.0015%). In the amplifier’s
data sheet, the settling at 0.1% to 0.01% is more commonly
specified. It could significantly differ from the settling time at
16-bit level and, therefore, it should be verified prior to the
driver selection. The tiny op amp AD8021, which combines
ultralow noise and a high gain bandwidth, meets this settling
time requirement even when used with a high gain up to 13.
The noise generated by the driver amplifier needs to be kept
as low as possible in order to preserve the SNR and transition
noise performance of the AD7663. The noise coming from
the driver is first scaled down by the resistive scaler according
to the analog input voltage range used, and is then filtered by
the AD7663 analog input circuit one-pole, low-pass filter
made by (R/2 + R1) and CS. The SNR degradation due to
the amplifier is
SNR
f
Ne
FSR
LOSS
dB
N
=
+
20
28
784
2
25
3
2
log
.
–
p
where:
f–3 dB is the –3 dB input bandwidth in MHz of the AD7663
(0.8 MHz) or the cut-off frequency of the input filter
if any used (0 V to 2.5 V range).
N
is the noise factor of the amplifier (1 if in buffer
configuration).
eN
is the equivalent input noise voltage of the op amp
in nV/Hz
1/2.
FSR is the full-scale span (i.e., 5 V for ±2.5 V range).
For instance, when using the 0 V to 2.5 V range, a driver
like the AD8610 with an equivalent input noise of 6 nV/
÷Hz
and configured as a buffer, thus with a noise gain of 1, the
SNR degrades by only 0.24 dB.
The driver needs to have a THD performance suitable to
that of the AD7663. TPC 10 gives the THD versus frequency
that the driver should preferably exceed.
The AD8021 meets these requirements and is usually appropri-
ate for almost all applications. The AD8021 needs an external
compensation capacitor of 10 pF. This capacitor should have good
linearity as an NPO ceramic or mica type.
The AD8022 could also be used where a dual version is needed
and gain of 1 is used.
The AD829 is another alternative where high frequency (above
100 kHz) performance is not required. In a gain of 1, it requires
an 82 pF compensation capacitor.
The AD8610 is also another option where low bias current is
needed in low frequency applications.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7663ACPZRL | 功能描述:IC ADC 16BIT CMOS 5V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7663AST | 制造商:Analog Devices 功能描述:ADC Single SAR 250ksps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:16-BIT, 250K SPS CMOS A/D CONVERTER - Bulk 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD7663ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 250ksps 16-bit Parallel/Serial 48-Pin LQFP T/R |
| AD7663ASTZ | 功能描述:IC ADC 16BIT CMOS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7663ASTZ | 制造商:Analog Devices 功能描述:IC, ADC, 16BIT, 250KSPS, LQFP-48 |
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