參數(shù)資料
型號(hào)： AD7660ASTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/20頁(yè)
文件大小： 0K
描述： IC ADC 16BIT UNIPOLAR 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 25mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)偽差分，單極
配用： EVAL-AD7660CBZ-ND - BOARD EVALUATION FOR AD7660
REV. D
AD7660
–16–
Usually, because the AD7660 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. This makes the Master Read after conversion the
most recommended Serial Mode when it can be used. In this
mode, it should be noted that, unlike in other modes, the signal
BUSY returns LOW after the 16 data bits are pulsed out and
not at the end of the conversion phase, which results in a longer
BUSY width.
In Read-during-Conversion Mode, the serial clock and data
toggle at appropriate instants, which minimizes potential
feedthrough between digital activity and the critical conversion
decisions.
SLAVE SERIAL INTERFACE
External Clock
The AD7660 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/
INT pin is held
HIGH. In this mode, several methods can be used to read the
data. When
CS and RD are both LOW, the data can be read
after each conversion or during the following conversion. The
external clock can be either a continuous or discontinuous clock.
A discontinuous clock can be either normally HIGH or normally
LOW when inactive. Figures 18 and 20 show the detailed timing
diagrams of these methods. Usually, because the AD7660 has a
longer acquisition phase than the conversion phase, the data are
read immediately after conversion.
While the AD7660 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is par-
ticularly important during the second half of the conversion
phase because the AD7660 provides error correction circuitry that
can correct for an improper bit decision made during the first half
of the conversion phase. For this reason, it is recommended
that when an external clock is being provided, it is a discon-
tinuous clock that is toggling only when BUSY is LOW or, more
importantly, that it does not transition during the latter half of
BUSY HIGH.
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 18 shows the detailed timing diagrams of this method. After
a conversion is complete, indicated by BUSY returning LOW,
the result of this conversion can be read while both
CS and RD are
LOW. The data is shifted out, MSB first, with 16 clock pulses and
is valid on both the rising and falling edge of the clock.
Among the advantages of this method, the conversion performance
is not degraded because there are no voltage transients on the
digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both slow digital host inter-
face and the fastest serial reading.
Finally, in this mode only, the AD7660 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when it is desired as it is, for
instance, in isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift out
the data on SDOUT. Therefore, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter on
the next SCLK cycle. Up to 20 AD7660s running at 100 kSPS
can be daisy-chained using this method.
SCLK
SDOUT
RDC/SDIN
BUSY
DATA OUT
AD7660
#1
(DOWNSTREAM)
BUSY OUT
CNVST
CS
SCLK
AD7660
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
CNVST
CS
Figure 19. Two AD7660s in a Daisy-Chain Configuration
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
CS
BUSY
SDIN
EXT/
INT = 1
INVSCLK = 0
t35
t36 t37
t31
t32
t16
t33
X15
X14
X
12
3
14
15
1617
18
RD = 0
t34
Figure 18. Slave Serial Data Timing for Reading (Read after Convert)
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