參數(shù)資料
型號: AD7660ACPZRL
廠商: Analog Devices Inc
文件頁數(shù): 5/20頁
文件大小: 0K
描述: IC ADC 16BIT UNIPOLAR 48LFCSP
標準包裝: 1
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 100k
數(shù)據接口: 串行,并聯(lián)
轉換器數(shù)目: 1
功率耗散(最大): 25mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 標準包裝
輸入數(shù)目和類型: 2 個偽差分,單極
其它名稱: AD7660ACPZRLDKR
REV. D
AD7660
–13–
The AD8519, OP162, or the OP184 meet these requirements
and are usually appropriate for almost all applications. As an
alternative, in very high speed and noise-sensitive applications,
the AD8021 with an external compensation capacitor of 10 pF
or the AD829 with an external compensation capacitor of 82 pF
can be used. This capacitor should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
+1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.
Voltage Reference Input
The AD7660 uses an external 2.5 V voltage reference.
The voltage reference input REF of the AD7660 has a dynamic
input impedance; it should therefore be driven by a low impedance
source with an efficient decoupling between REF and REFGND
inputs. This decoupling depends on the choice of the voltage
reference but usually consists of a 1
mF ceramic capacitor and a
low ESR tantalum capacitor connected to the REF and REFGND
inputs with minimum parasitic inductance. 47
mF is an appropriate
value for the tantalum capacitor when used with one of the
recommended reference voltages:
∑ The low noise, low temperature drift ADR421 and AD780
voltage references
∑ The low power ADR291 voltage reference
∑ The low cost AD1582 voltage reference
For applications using multiple AD7660s, it is more effective to
buffer the reference voltage with a low noise, very stable op amp
like the AD8031.
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference that directly affects the full-scale
accuracy if this parameter matters. For instance, a
±15 ppm/∞C
tempco of the reference changes the full scale by
±1 LSB/∞C.
VREF , as mentioned in the specification table, could be increased
to AVDD – 1.85 V. The benefit here is the increased SNR
obtained as a result of this increase. Since the input range is
defined in terms of VREF, this would essentially increase the
range to make it a
±3 V input range with an AVDD above 4.85 V.
The theoretical improvement as a result of this increase in
reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical
quantization noise, however, the observed improvement is
approximately 1 dB. The AD780 can be selected with a 3 V
reference voltage.
Power Supply
The AD7660 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and 5.25 V.
To reduce the number of supplies needed, the digital core
(DVDD) can be supplied through a simple RC filter from the
analog supply, as shown in Figure 5. The AD7660 is independent
of power supply sequencing and thus free from supply voltage
induced latch-up. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 9.
INPUT FREQUENCY – Hz
PSRR
dB
–80
1k
10k
100k
1M
–75
–70
–65
–60
–55
–50
Figure 9. PSRR vs. Frequency
POWER DISSIPATION VS. THROUGHPUT
The AD7660 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows a significant
power saving when the conversion rate is reduced, as shown in
Figure 10. This feature makes the AD7660 ideal for very low
power battery applications. It should be noted that the digital
interface remains active even during the acquisition phase. To
reduce the operating digital supply currents even further, the
digital inputs need to be driven close to the power rails (i.e.,
DVDD and DGND for all inputs except EXT/
INT, INVSYNC,
INVSCLK, RDC/SDIN, and OVDD or OGND for the last
four inputs.
THROUGHPUT – SPS
10
100000
POWER
DISSIPATION
W
100000
1000
10000
100
1
10
100
1000
10000
Figure 10. Power Dissipation vs. Sample Rate
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