參數(shù)資料
型號(hào)： AD7658BSTZ-REEL
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 250 kSPS, 6-Channel,Simultaneous Sampling, Bipolar 12/14/16-Bit ADC
中文描述： 6-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP64
封裝： ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁(yè)數(shù)： 17/25頁(yè)
文件大?。?/td> 308K
代理商： AD7658BSTZ-REEL
Preliminary Technical Data
AD7658/AD7657/AD7656
INTERFACE SECTION
The AD7658/AD7657/AD7656 provides two interface options,
a parallel interface and a high speed serial interface. The
required interface mode is selected via the SER/PAR pin. The
parallel interface can operate in word (W/B = 1) or byte (W/B =
0) mode. The interface modes are discussed in the following
sections.
Parallel Interface (SER/PAR = 0)
The AD7658/AD7657/AD7656 consist of six 12/14/16-bit
ADCs. A simultaneous sample of all six ADCs can be
performed by connecting all three CONVST pins together,
CONVSTA, CONVSTB, CONVSTC. The rising edge of
CONVSTX initiates simultaneous conversions on the selected
ADCs. The AD7658/AD7657/AD7656 contains an on-chip
oscillator that is used to perform the conversions. The
conversion time, t
CONV
,
is 3 μs. The BUSY signal goes low to
indicate the End of Conversion. The falling edge of the BUSY
signal is used to place the track-and-hold into track mode. The
AD7658/AD7657/AD7656 also allow the six ADCs to be
simultaneously converted in pairs by pulsing the three
CONVST pins independently. CONVSTA is used to initiate
simultaneous conversions on V1 and V2, CONVSTB is used to
initiate simultaneous conversions on V3 and V4, and
CONVSTC is used to initiate simultaneous conversions on V5
and V6. The conversion results from the simultaneously
sampled ADCs are stored in the output data registers.
Rev. PrI | Page 17 of 25
Data can be read from the AD7658/AD7657/AD7656 via the
parallel data bus with standard CS and RD signals (W/B = 0).
To read the data over the parallel bus SER/PAR should be tied
low. The CS and RD input signals are internally gated to enable
the conversion result onto the data bus. The data lines DB0 to
DB15 leave their high impedance state when both CS and RD
are logic low. The CS signal can be permanently tied low and
the RD signal can be used to access the conversion results. A
read operation can take place after the BUSY signal goes low.
The number of read operations required will depend on the
number of ADCs that were simultaneously sampled, see Figure
5. If CONVSTA and CONVSTB were brought low
simultaneously, four read operations are required to obtain the
conversion results from V1, V2, V3 and V4. The conversion
results will be output in ascending order. For the AD7657 DB15
and DB14 will contain two leading zeros and DB[13:0] will
output the 14-bit conversion result. For the AD7658 DB[15:12]
will contain four leading zeros and DB[11:0] will output the 12-
bit conversion result.
If there is only an 8-bit bus available the
AD7658/AD7657/AD7656 interface can be configured to
operate in BYTE mode (W/B= 1). In this configuration the
DB7/HBEN/DCEN pin takes on its HBEN function. The
conversion results from the AD7658/AD7657/AD7656 can be
accessed in two read operations with 8-bits of data provided on
DB15 to DB8 for each of the read operations, See Figure 6. The
HBEN pin determines whether the read operation accesses the
high byte or the low byte of the 12/14/16-bit conversion result
first. To always access the low byte first on DB15 to DB8, the
HBEN pin should be tied low. To always access the high byte
first on DB15 to DB8 then the HBEN pin should be tied high. In
BYTE mode when all three CONVST pins are pulsed together
to initiate simultaneous conversions on all six ADCs, twelve
read operations are necessary to read back the six 12/14/16-bit
conversion results when operating in BYTE mode. DB[6:0]
should be left unconnected in byte mode.
The AD7658/AD7657/AD7656 allow the option of reading
during a conversion. If for example, a simultaneous conversion
had occurred on V1 and V2 by pulsing the CONVSTA pin. The
processor will next read the conversion results from the
AD7658/AD7657/AD7656. During the read operation after the
BUSY signal has gone low further simultaneous conversions can
be initiated by pulsing the CONVST pins. However to achieve
the specified performance from the AD7658/AD7657/AD7656
reading after the conversion is recommended.
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