參數(shù)資料
型號(hào)： AD7657BSTZ-REEL
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 250 kSPS, 6-Channel,Simultaneous Sampling, Bipolar 12/14/16-Bit ADC
中文描述： 6-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP64
封裝： ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁(yè)數(shù)： 13/25頁(yè)
文件大?。?/td> 308K
代理商： AD7657BSTZ-REEL
Preliminary Technical Data
AD7658/AD7657/AD7656
Rev. PrI | Page 13 of 25
pin. When SER/PAR =1 this pin takes on its SCLK input function, obtaining the read serial clock
for the serial transfer.
Data bit 7/ High Byte Enable/ Daisy Chain Enable. When operating in Parallel Word mode
(SER/PAR = 0 and W/B = 1) this pin takes on its Data bit 7 function. When operating in Parallel
Byte mode (SER/PAR = 0 and W/B = 0), this pin takes on its HBEN function. When in this mode
and the HBEN pin is a logic high, the data will be output MSB byte first on DB[15:8]. When the
HBEN pin is a logic low the data will be output LSB byte first on DB[15:8]. When operating in
Serial mode (SER/PAR = 1) this pin takes on its DCEN function. When DCEN pin is a logic high
the part will operate in Daisy Chain mode with DB[5:3] taking on their DCIN[A:C] function.
Data Bit [8]/Serial Data Output A. When SER/PAR =0, this pin acts as a three-state Parallel
Digital Output pin. When SER/PAR =1 and SEL A = 1, this pin takes on its DOUT A function.
Data Bit [9]/Serial Data Output B. When SER/PAR =0, this pin acts as a three-state Parallel
Digital Output pin. When SER/PAR =1 and SEL B = 1, this pin takes on its DOUT B function. This
configures the serial interface to have two SDATA output lines.
Data Bit [10]/Serial Data Output C. When SER/PAR =0, this pin acts as a three-state Parallel
Digital Output pin. When SER/PAR =1 and SEL C = 1, this pin takes on its DOUT C function. This
configures the serial interface to have three SDATA output lines.
Data Bit [11]/Digital Ground. When SER/PAR =0, this pin acts as a three-state Parallel Digital
Output pin. When SER/PAR =1, this pin should be tied to DGND.
Data Bit [12:15]. SER/PAR =0 these pins act as a three-state parallel Digital Input/Output pins.
When CS and RD are low these pins are used to output the conversion result. When CS and WR
are low these pins are used to write to the Control Register. When SER/PAR =1 these pins
should be tied to DGND.
Data Bit [14]/ REFBUF ENABLE/DISABLE. When SER/PAR =0, this pin acts as a three-state Digital
Input/output pin. When SER/PAR =1, this pin can be used to enable or disable the internal
reference buffers.
Reset Input. When set to a logic high, reset the AD7658/AD7657/AD7656. The Current
conversion if any is aborted. Internal register is set to all 0’s. If not in use, this pin could be tied
low. In Hardware mode the AD7658/AD7657/AD7656 will be configured depending on the
logic levels on the hardware select pins. When operating in software mode a reset pulse is
required afterpower up to select the default settings in the Internal register. (See Register
section)
Analog Input Range Selection. Logic input. The polarity on this pin will determine what input
range the analog input channels will have. When this pin is a logic 1 at the falling edge of
BUSY then range for the next conversion is ± 2 x VREF. When this pin is a logic 0 at the falling
edge of BUSY then range for the next conversion is ± 4 x VREF.
Positive power supply voltage. This is the positive supply voltage for the Analog Input section.
10 μF and 100 nF decoupling capacitors should be placed on the VDD pin.
Negative power supply voltage. This is the negavtive supply voltage for the Analog Input
section. 10 μF and 100 nF decoupling capacitors should be placed on the VSS pin.
Standby mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY
pin is high for normal operation and low for standby operation.
Hardware/Software Select Input. Logic Input. When SER/PAR =0 and this pin is a logic low the
AD7658/AD7657/AD7656 operates in Hardware select mode. The ADC pairs to be
simultaneously sampled are selected by the CONVST pins. When SER/PAR =0 this pin is a logic
high the ADC pairs to be simultaneously sampled are selected by writing to the control
register.
Word/Byte Input. When this pin is a logic low data can be transfered to and from the
AD7658/AD7657/AD7656 using the parallel data lines DB[15:0]. When this pin is a logic high
Byte mode is enabled. In this mode data is transferred using data lines DB[15:8], DB[7] takes on
its HBEN function. To obtain the 12/14/16-bit conversion result two byte reads are required.
DB[7]/HBEN/DCEN
DB[8]/DOUT A
DB[9]/DOUT B
DB[10]/DOUT C
DB[11]/DGND
DB[12:13], DB[15]
DB[14]/REFBUF
EN/DIS
RESET
RANGE
VDD
VSS
STBY
H/S SEL
W/B
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AD7658 制造商:AD 制造商全稱:Analog Devices 功能描述:250 kSPS, 6-Channel,Simultaneous Sampling, Bipolar 12/14/16-Bit ADC
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