
REV. 0
AD7655
–11–
CIRCUIT INFORMATION
The AD7655 is a very fast, low power, single-supply, precise
4-channel 16-bit analog-to-digital converter (ADC).
The AD7655 provides the user with two on-chip track-and-hold,
successive approximation ADCs that do not exhibit any pipeline
or latency, making it ideal for multiple multiplexed channel
applications.
The AD7655 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP or in a tiny 48-lead LFCSP package that combines
space savings and allows flexible configurations as either serial
or parallel interface. The AD7655 is pin-to-pin compatible with
PulSAR ADCs.
Modes of Operation
The AD7655 features two modes of operation, normal and impulse.
Each of these modes is more suitable for specific applications.
The normal mode is the fastest mode (1 MSPS). Except when
it is powered down (PD HIGH), the power dissipation is almost
independent of the sampling rate.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput in
this mode is 888 kSPS. When operating at 20 kSPS, for example,
it typically consumes only 2.6 mW. This feature makes the
AD7655 ideal for battery-powered applications.
Transfer Functions
The AD7655 data format is straight binary. The ideal transfer
characteristic for the AD7655 is shown in Figure 3 and Table II.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT
+FS – 1.5 LSB
+FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
A
Figure 3. ADC Ideal Transfer Function
Table II. Output Codes and Ideal Input Voltages
Analog
Input V
REF
= 2.5 V
Digital Output
Code (Hex)
D
escription
FSR
–
1 LSB
FSR
–
2 LSB
Midscale + 1 LSB
Midscale
Midscale
–
1 LSB
–
FSR + 1 LSB
–
FSR
4.999924 V
4.999847 V
2.500076 V
2.5 V
2.499924 V
–
76.29
m
V
0 V
FFFF
1
FFFE
8001
8000
7FFF
0001
0000
2
NOTES
1
This is also the code for overrange analog input (V
INx
–
V
INxN
above
2 (V
REF
–
V
REFGND
)).
2
This is also the code for underrange analog input (V
INx
below V
INxN
).