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| 型號： | AD7655ACPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 4CHAN 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 135mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極 |
| 配用： | EVAL-AD7655CBZ-ND - BOARD EVALUATION FOR AD7655 |
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AD7655
Rev. B | Page 19 of 28
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the other channel’s conversion, or during the following
When the data is read during the conversion, however, it is
recommended that it is read only during the first half of the
conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
DATA BUS
t18
t19
BUSY
CURRENT
CONVERSION
CS
RD
03536-024
Figure 24. Slave Parallel Data Timing for Reading (Read after Convert)
PREVIOUS
CONVERSION
t1
t3
t18
t19
t4
BUSY
DATA BUS
t13
t11
t12
t10
CS = 0
EOC
CNVST, RD
03536-025
Figure 25. Slave Parallel Data Timing for Reading (Read During Convert)
8-Bit Interface (Master or Slave)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 26, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped, the
LSB is output on D[15:8], and the MSB is output on D[7:0]. By
connecting BYTESWAP to an address line, the 16-bit data can
be read in 2 bytes on either D[15:8] or D[7:0].
BYTESWAP
PINS D[15:8]
PINS D[7:0]
HI-Z
HIGH BYTE
LOW BYTE
HIGH BYTE
HI-Z
t18
t19
CS
RD
03536-026
Figure 26. 8-Bit Parallel Interface
Channel A/B Output
The A/B input controls which channel’s conversion results
(INAx or INBx) are output on the data bus. The function-ality
of A/B is detailed in Figure 27. When high, the data from
Channel A is available on the data bus. When low, the data from
Channel B is available on the bus. Note that in parallel reading
mode, Channel A can be read immediately after the end of
conversion (EOC), while Channel B is still in its converting
phase. However, in any of the serial reading modes Channel A
data is updated only after Channel B conversion.
t18
t20
CS
DATA BUS
RD
HI-Z
A/B
HI-Z
CHANNEL A
CHANNEL B
03536-027
Figure 27. A/B Channel Reading
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| AD7655AST | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7655 LQFP48 |
| AD7655ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP T/R |
| AD7655ASTZ | 功能描述:IC ADC 16BIT 1MSPS QUAD 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7655ASTZ | 制造商:Analog Devices 功能描述:CONVERTER A/D ((NW)) |
| AD7655ASTZRL | 功能描述:IC ADC 16BIT 4CHAN 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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