參數(shù)資料
型號: AD7653ACPZRL
廠商: Analog Devices Inc
文件頁數(shù): 27/28頁
文件大小: 0K
描述: IC ADC 16BIT UNIPOLAR 48LFCSP
標準包裝: 2,500
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 1M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 145mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個偽差分,單極
配用: EVAL-AD7653CBZ-ND - BOARD EVALUATION FOR AD7653
AD7653
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
NC
BYTESWAP
OB/2C
WARP
IMPULSE
NC = NO CONNECT
SER/PAR
D0
D1
BUSY
D15
D14
D13
AD7653
D3/DIVSCLK1
D12
D4
/E
X
T
/INT
D
5
/IN
VSYN
C
D6/INVSCL
K
D7
/RDC/S
D
IN
OGND
OVDD
DV
DD
DGND
D8
/S
DOUT
D9
/S
CLK
D
10/SYN
C
D1
1
/RDE
RROR
P
DBUF
P
DRE
F
RE
FBUFIN
TEMP
AV
DD
IN
AGND
NC
INGND
RE
FGND
RE
F
02966-0-002
D2/DIVSCLK0
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 36,
41, 42
AGND
P
Analog Power Ground Pin.
2, 44
AVDD
P
Input Analog Power Pin. Nominally 5 V.
3, 40
NC
No Connect.
4
BYTESWAP
DI
Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5
OB/2C
DI
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift
register.
6
WARP
DI
Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest
mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in
order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
7
IMPULSE
DI
Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power
mode. In this mode, the power dissipation is approximately proportional to the sampling rate.
8
SER/PAR
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial
interface mode is selected and some bits of the DATA bus are used as a serial port.
9, 10
D[0:1]
DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
11, 12
D[2:3]or
DIVSCLK[0:1]
DI/O
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),
these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that
clocks the data output. In other serial modes, these pins are not used.
13
D4 or
EXT/INT
DI/O
When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choos-
ing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is
selected on the SCLK output. With EXT/INT set to logic HIGH, output data is synchronized to an
external clock signal connected to the SCLK input.
14
D5 or
INVSYNC
DI/O
When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the
SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When
HIGH, SYNC is active LOW.
Rev. A | Page 8 of 28
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