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參數(shù)資料
| 型號(hào)： | AD7643BSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 19/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT DIFFER W/REF 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | EVAL-AD7643CBZ-ND - BOARD EVALUATION FOR AD7643 |
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AD7643
Rev. 0 | Page 26 of 28
MICROPROCESSOR INTERFACING
The AD7643 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The
AD7643 is designed to interface with a parallel 8-bit or 16-bit
wide interface or with a general-purpose serial port or I/O ports
on a microcontroller. A variety of external buffers can be used
with the AD7643 to prevent digital noise from coupling into the
ADC. The SPI Interface (ADSP-219x) section illustrates the use
of the AD7643 with the ADSP-219x SPI-equipped DSP.
SPI Interface (ADSP-219x)
Figure 41 shows an interface diagram between the AD7643 and
an SPI-equipped DSP, the ADSP-219x. To accommodate the
slower speed of the DSP, the AD7643 acts as a slave device and
data must be read after conversion. This mode also allows the
daisy-chain feature. The convert command can be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with three SPI byte access. The reading process can be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
peripheral interface (SPI) on the ADSP-219x is configured for
master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock
phase bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) =
00 by writing to the SPI control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mbps, allowing it to read an ADC result in less
than 1 μs. When a higher sampling rate is desired, it is
recommended to use one of the parallel interface modes.
BUSY
CS
SDOUT
SCLK
CNVST
AD7643
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx OR TFSx
ADSP-219x1
DVDD
MODE0
MODE1
EXT/INT
RD
INVSCLK
1ADDITIONAL PINS OMITTED FOR CLARITY.
06
02
4-
0
41
Figure 41. Interfacing the AD7643 to ADSP-219x
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