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參數(shù)資料
| 型號： | AD7641ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 2 MSPS SAR ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 324K |
| 代理商： | AD7641ASTRL |
Preliminary Technical Data
AD7641
INTERFACES
DIGITAL INTERFACE
The AD7641 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7641 digital interface also accommodates both 2.5V, 3.3V or
5V logic with OVDD either at 2.5V or 3.3V. OVDD defines the
logic high output voltage. In most applications, the OVDD
supply pin of the AD7641 is connected to the host system
interface 2.5V or 3.3V digital supply. Finally, except in 18 bit
interface mode, by using the OB/2C input pin, both two’s
complement or straight binary coding can be used.
Rev. Pr E | Page 17 of 24
The two signals CS and RD control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7641 in
multi-circuits applications and is held low in a single AD7641
design. RD is generally used to enable the conversion result on
the data bus.
t1
t3
t4
t11
CNVST
BUSY
DATA
BUS
CS = RD = 0
t10
PREVIOUS CONVERSION DATA
NEW DATA
Figure 15. Master Parallel Data Timing for Reading (Continuous Read)
PARALLEL INTERFACE
The AD7641 is configured to use the parallel interface with
either a 18-bit, 16-bit or 8-bit bus width according to the Table
6. The data can be read either after each conversion, which is
during the next acquisition phase, or during the following
conversion as shown, respectively, in Figure 16 and Figure 17.
When the data is read during the conversion, however, it is
recommended that it is read only during the first half of the
conversion phase. That avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry. Please refer to Table 6 for a
detailed description of the different options available.
CURRENT
CONVERSION
BUSY
DATA
BUS
CS
RD
t
12
t
13
Figure 16. Slave Parallel Data Timing for Read (Read After Convert)
t
1
t
3
t
4
CS = 0
CNVST, RD
BUSY
PREVIOUS
CONVERSION
t
12
t
13
DATA
BUS
Figure 17. Slave Parallel Data Timing for Reading (Read During Convert)
CS
BYTESWAP
Pins D[15:8]
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
t12
t12
t13
Pins D[7:0]
RD
Figure 18. 8-Bit and 16-Bit Parallel Interface
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