參數(shù)資料
型號(hào)： AD7631BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 18BIT 250KSPS BIP 48LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
位數(shù)： 18
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 120mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
Data Sheet
AD7631
Rev. B | Page 23 of 32
Power Sequencing
The AD7631 requires sequencing of the AVDD and DVDD
supplies. AVDD should come up prior to or simultaneously
with DVDD. This can be achieved using the configuration in
Figure 27 or sequencing the supplies in that manner. The
other supplies can be sequenced as desired as long as absolute
maximum ratings are observed. The AD7631 is very insensitive
to power supply variations on AVDD over a wide frequency
range, as shown in Figure 33.
30
35
40
45
50
55
60
65
70
75
1
10
100
1000
10000
0
65
88
-033
FREQUENCY (kHz)
PSR
R
(
d
B
)
Figure 33. AVDD PSRR vs. Frequency
Power Dissipation vs. Throughput
In impulse mode, the AD7631 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows
a significant power savings when the conversion rate is reduced
(see Figure 34). This feature makes the AD7631 ideal for very
low power, battery-operated applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital supply
currents even further, drive the digital inputs close to the power
rails, that is, OVDD and OGND.
1
10
100
1000
1
10
100
1000
10000
100000
1000000
PDREF = PDBUF = HIGH
0
65
88
-0
34
SAMPLING RATE (kSPS)
PO
W
E
R
D
ISSI
P
A
T
IO
N
(
m
W
)
Figure 34. Power Dissipation vs. Sample Rate
Power Down
Setting PD = high powers down the AD7631, thus reducing
supply currents to their minimums, as shown in Figure 23.
When the ADC is in power-down, the current conversion
(if any) is completed and the digital bus remains active. To
further reduce the digital supply currents, drive the inputs to
OVDD or OGND.
Power-down can also be programmed with the configuration
register. See the Software Configuration section for details. Note
that when using the configuration register, the PD input is a don’t
care and should be tied to either high or low.
CONVERSION CONTROL
The AD7631 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion. A
detailed timing diagram of the conversion process is shown in
Figure 35. Once initiated, it cannot be restarted or aborted, even
by the power-down input, PD, until the conversion is complete.
The CNVST signal operates independently of CS and RD
signals.
BUSY
MODE
CONVERT
ACQUIRE
CONVERT
CNVST
t1
t2
t4
t3
t5
t6
t7
t8
0
6588-
035
Figure 35. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot, undershoot, or ringing.
The CNVST trace should be shielded with ground and a low value
(such as 50 Ω) serial resistor termination should be added close
to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 27.
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