參數(shù)資料
型號: AD7631
廠商: Analog Devices, Inc.
英文描述: 18-Bit 250/670 kSPS PulSAR Bipolar Programmable Inputs ADC
中文描述: 18位六百七十○分之二百五十○kSPS的PulSAR系列雙極性輸入ADC的可編程
文件頁數(shù): 7/14頁
文件大小: 192K
代理商: AD7631
Preliminary Technical Data
AD7631/AD7634
Parameter
Rev. PrC | Page 7 of 14
Symbol
Min
Typ
Max
Unit
BUSY High in Master Serial Read after Convert
4
CNVST Low to SYNC Asserted Delay (all Modes)
AD7631
AD7634 (Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL INTERFACE MODES
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
1
In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
3
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
4
In serial master read during convert mode. See
Error! Reference source not found.
for serial master read after convert mode timing specifications.
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum (Warp mode)
BUSY High Width Maximum (Normal mode)
BUSY High Width Maximum (Impulse mode)
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
5
1
5
5
12.5
5
5
See
Table 4
TBD
TBD
25
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
t
18
t
19
t
19
t
20
t
21
t
22
t
23
t
24
t
28
t
28
t
28
0
0
3
25
40
12
7
4
2
3
1.75
2
2.25
0
1
17
60
80
22
21
18
4
60
2.5
2.75
3
1
0
17
120
160
50
49
18
30
140
4
4.25
4.5
1
1
17
240
320
100
99
18
89
300
7
7.25
7.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
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