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參數(shù)資料
| 型號(hào)： | AD7626BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 10MSPS DIFF 32LFCSP |
| 設(shè)計(jì)資源： | Single-Ended-to-Differential High Speed Drive Circuit for 16-Bit, 10 MSPS AD7626 ADC (CN0105) |
| 特色產(chǎn)品： | AD7626 PulSAR Differential ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 10M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 170mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，雙極 |
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AD7626
Data Sheet
Rev. B | Page 22 of 28
DIGITAL INTERFACE
Conversion Control
All analog-to-digital conversions are controlled by the CNV±
signal. This signal can be applied in the form of a CNV+/CNV
LVDS signal, or it can be applied in the form of a 2.5 V CMOS
logic signal to the CNV+ pin. The conversion is initiated by the
rising edge of the CNV± signal.
After the AD7626 is powered up, the first conversion result
generated is invalid. Subsequent conversion results are valid
provided that the time between conversions does not exceed
the maximum specification for tCYC.
The two methods for acquiring the digital data output of the
AD7626 via the LVDS interface are described in the following
sections.
Echoed-Clock Interface Mode
The digital operation of the AD7626 in echoed-clock interface
mode is shown in Figure 41. This interface mode, requiring
only a shift register on the digital host, can be used with many
digital hosts (such as FPGA, shift register, and microprocessor).
It requires three LVDS pairs (D±, CLK±, and DCO±) between
each AD7626 and the digital host.
The clock DCO± is a buffered copy of CLK± and is synchronous
to the data, D±, which is updated on the falling edge of DCO +
(tD). By maintaining good propagation delay matching between
D± and DCO± through the board and the digital host, DCO
can be used to latch D± with good timing margin for the shift
register.
Conversions are initiated by a rising edge CNV± pulse. The
CNV± pulse must be returned low (≤ tCNVH maximum) for
valid operation. After a conversion begins, it continues until
completion. Additional CNV± pulses are ignored during the
conversion phase. After the time, tMSB, elapses, the host should
begin to burst the CLK±. Note that, tMSB, is the maximum time
for the MSB of the new conversion result and should be used as
the gating device for CLK±. The echoed clock, DCO±, and the
data, D, are driven in phase with D± being updated on the
falling edge of DCO+; the host should use the rising edge of
DCO+ to capture D±. The only requirement is that the 16
CLK± pulses finish before the time (tCLKL) elapses of the next
conversion phase or the data is lost. From the tCLKL to tMSB, D±
and DCO± are driven to 0. Set CLK± to idle low between CLK±
bursts.
CLK+
tCYC
16
15
CNV+
116
15
2
123
tCNVH
tCLKL
DCO+
16
15
1
16
15
2
1
23
D+
SAMPLE N
SAMPLE N + 1
D–
D15
N
D14
N
D1
N
CLK–
CNV–
DCO–
D0
N – 1
ACQUISITION
tDCO
tD
tCLK
0
tMSB
D1
N – 1
D15
N + 1
D14
N + 1
D0
N
0
D13
N + 1
tCLKD
0
76
48
-10
3
Figure 41. Echoed-Clock Interface Mode Timing Diagram
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| AD7626BCPZ-RL7 | 功能描述:IC ADC 16BIT 10MSPS DIFF 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7628 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS Dual 8-Bit Buffered Multiplying DAC |
| AD7628BFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| AD7628BN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| AD7628BQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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