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參數(shù)資料
| 型號： | AD7623ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 1.33MSPS DFF 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1.33M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 55mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7623CBZ-ND - BOARD EVALUATION FOR AD7623 |
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AD7623
Rev. 0 | Page 21 of 28
INTERFACES
DIGITAL INTERFACE
The AD7623 has a versatile digital interface that can be set up
as either a serial or parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The
AD7623 digital interface also accommodates 2.5 V, 3.3 V, or 5 V
logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the
logic high output voltage. In most applications, the OVDD
supply pin of the AD7623 is connected to the host system
interface 2.5 V or 3.3 V digital supply. Finally, by using the
OB/2C input pin, both twos complement or straight binary
coding can be used.
The two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7623 in
multicircuit applications and is held low in a single AD7623
design. RD is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7623 and generate a
fast initialization. A rising edge on RESET aborts the current
conversion (if any) and tristates the data bus. The falling edge of
RESET clears the data bus and engages the initialization process
indicated by pulsing BUSY high. Conversions can take place
after the falling edge of BUSY. Refer to Figure 32 for the RESET
timing details.
05574-032
RESET
DATA
BUSY
CNVST
t38
t39
t8
t9
Figure 32. RESET Timing
PARALLEL INTERFACE
The AD7623 is configured to use the parallel interface when
SER/PAR is held low.
Master Parallel Interface
Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 33 details the timing for this mode.
05574-
033
t1
BUSY
DATA
BUS
PREVIOUS CONVERSION DATA
NEW DATA
CNVST
CS = RD = 0
t10
t4
t11
t3
Figure 33. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 34 and
Figure 35, respectively. When the data is read during the
conversion, it is recommended that it is read-only during the
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.
05574-034
CURRENT
CONVERSION
t13
t12
BUSY
DATA
BUS
RD
CS
Figure 34. Slave Parallel Data Timing for Reading (Read After Convert)
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