參數(shù)資料
型號(hào)： AD7608BSTZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 13/32頁
文件大小： 0K
描述： IC DAS W/ADC 18BIT 8CH 64LQFP
標(biāo)準(zhǔn)包裝： 1,500
類型： 數(shù)據(jù)采集系統(tǒng)（DAS），ADC
分辨率（位）： 18 b
采樣率（每秒）： 200k
數(shù)據(jù)接口： DSP，MICROWIRE?，并聯(lián)，QSPI?，串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 2.3 V ~ 5.25 V，4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
AD7608
Data Sheet
Rev. A | Page 20 of 32
Analog Input Antialiasing Filter
An analog antialiasing filter (a second-order Butterworth) is also
provided on the AD7608. Figure 34 and Figure 35 show the
frequency and phase response, respectively, of the analog
antialiasing filter. In the ±5 V range, the 3 dB frequency is
typically 15 kHz. In the ±10 V range, the 3 dB frequency is
typically 23 kHz.
5
0
–5
–10
–15
–20
–25
–30
–35
–40
100
1k
10k
100k
AT
T
E
NUAT
IO
N
(
d
B)
INPUT FREQUENCY (Hz)
08938-
135
±10V RANGE
±5V RANGE
AVCC, VDRIVE = 5V
fSAMPLE = 200kSPS
TA = 25°C
±10V RANGE
0.1dB
3dB
–40
10,303Hz 24,365Hz
+25
9619Hz
23,389Hz
+85
9326Hz
22,607Hz
±5V RANGE
0.1dB
3dB
–40
5225Hz
16,162Hz
+25
5225Hz
15,478Hz
+85
4932Hz
14,990Hz
Figure 34. Analog Antialiasing Filter Frequency Response
08938-
033
18
16
14
12
10
8
6
4
2
0
–2
100
100k
10k
1k
PH
A
SE
D
EL
A
Y
(
s
)
INPUT FREQUENCY (Hz)
AVCC, VDRIVE = 5V
fSAMPLE = 200kSPS
TA = 25°C
±5V RANGE
±10V RANGE
Figure 35. Analog Antialiasing Filter Phase Response
Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7608 allow the ADC
to accurately acquire an input sine wave of full-scale amplitude
to 18-bit resolution. The track-and-hold amplifiers sample
their respective inputs simultaneously on the rising edge of
CONVST x. The aperture time for track-and-hold (that is, the
delay time between the external CONVST x signal and the
track-and-hold actually going into hold) is well matched, by design,
across all eight track-and-holds on one device and from device
to device. This matching allows more than one AD7608 device
to be sampled simultaneously in a system.
The end of the conversion process across all eight channels is
indicated by the falling edge of BUSY; and it is at this point that the
track-and-holds return to track mode, and the acquisition time
for the next set of conversions begins.
The conversion clock for the part is internally generated, and
the conversion time for all channels is 4 s on the AD7608. The
BUSY signal returns low after all eight conversions to indicate the
end of the conversion process. On the falling edge of BUSY, the
track-and-hold amplifiers return to track mode. New data can
be read from the output register via the parallel, parallel byte, or
serial interface after BUSY goes low; or, alternatively, data from
the previous conversion can be read while BUSY is high. Reading
data from the AD7608 while a conversion is in progress has little
effect on performance and allows a faster throughput to be
achieved. In parallel mode at VDRIVE > 3.3 V, the SNR is reduced
by ~1.5 dB when reading during a conversion.
ADC TRANSFER FUNCTION
The output coding of the AD7608 is twos complement. The
designed code transitions occur midway between successive
integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is
FSR/262,144 for the AD7608. The ideal transfer characteristic
for the AD7608 is shown in Figure 36.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
–FS + 1/2LSB
0V – 1LSB
+FS – 3/2LSB
ADC
CO
DE
ANALOG INPUT
+FS
MIDSCALE
–FS
LSB
±10V RANGE +10V
0V
–10V
76.29V
±5V RANGE
+5V
0V
–5V
38.15V
+FS – (–FS)
218
LSB =
VIN
5V
REF
2.5V
±5V CODE =
× 131,072 ×
VIN
10V
REF
2.5V
±10V CODE =
× 131,072 ×
08938-
034
Figure 36. AD7608 Transfer Characteristic
The LSB size is dependent on the analog input range selected.
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