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參數(shù)資料
| 型號(hào)： | AD7575KPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT LC2MOS W/HOLD 20PLCC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 50k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 15mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
AD7575
–3–
REV. B
TIMING SPECIFICATIONS1
Limit at +25 C
Limit at TMIN, TMAX
Parameter
(All Versions)
(J, K, A, B Versions)
(S, T Versions)
Units
Conditions/Comments
t1
0
ns min
CS to RD Setup Time
t2
100
120
ns max
RD to BUSY Propagation Delay
t3
2
100
120
ns max
Data Access Time after
RD
t4
100
120
ns min
RD Pulse Width
t5
0
ns min
CS to RD Hold Time
t6
2
80
100
ns max
Data Access Time after
BUSY
t7
3
10
ns min
Data Hold Time
80
100
ns max
t8
0
ns min
BUSY to CS Delay
NOTES
1Timing specifications are sample tested at +25
°C to ensure compliance. All input control signals are specified with tr = tf = 20 ns (10% to 90% of +5 V)
and timed from a voltage level of 1.6 V.
2t
3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t
7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
(VDD = +5 V, VREF = +1.23 V, AGND = DGND = 0 V)
Test Circuits
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V
Digital Output Voltage to DGND . . . . . . –0.3 V, VDD + 0.3 V
CLK Input Voltage to DGND . . . . . . . . . –0.3 V, VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . . 0
°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . –25
°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . –55
°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300
°C
Power Dissipation (Any Package) to +75
°C . . . . . . . 450 mW
Derates above +75
°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7575 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
b High-Z to VOL
a. High-Z to VOH
Figure 1. Load Circuits for Data Access Time Test
Figure 2. Load Circuits for Data Hold Time Test
a. VOH to High-Z
b. VOL to High-Z
WARNING!
ESD SENSITIVE DEVICE
DGND
3k
100pF
DBN
DGND
3k
100pF
DBN
+5V
DGND
3k
10pF
DBN
DGND
3k
10pF
DBN
+5V
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