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參數(shù)資料
| 型號(hào)： | AD7568 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Octal 12-Bit DAC(LC2MOS八通道12位D/A轉(zhuǎn)換器) |
| 中文描述： | 八通道12位DAC（LC2MOS八通道12位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 251K |
| 代理商： | AD7568 |
AD7568
REV. B
–4–
ABSOLUT E MAX IMUM RAT INGS
1
(T
A
= +25
°
C unless otherwise noted)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
I
OUT 1
to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
I
OUT 2
to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V to V
DD
+0.3 V
V
RFB
, V
REF
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .
±
15 V
Input Current to Any Pin Except Supplies
2
. . . . . . . .
±
10 mA
Operating T emperature Range
Commercial Plastic (B Versions) . . . . . . . . –40
°
C to +85
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300
°
C
Power Dissipation (Any Package) to +75
°
C . . . . . . . . 250 mW
Derates above +75
°
C by . . . . . . . . . . . . . . . . . . . . 10 mW/
°
C
NOT ES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
T ransient currents of up to 100 mA will not cause SCR latch-up.
WARNING!
ESD SENSITIVE DEVICE
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7568 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN DE SCRIPT ION
Pin
Description
V
DD
DGND
AGND
V
REF
A – V
REF
H
R
FB
A – R
FB
H
I
OUT
A – I
OUT
H
AGND
Positive power supply. T his is +5 V
±
5%.
Digital Ground.
Analog Ground.
DAC reference inputs.
DAC feedback resistor pins.
DAC current output terminals.
T his pin connects to the back gates of the current steering switches. It should be connected to the signal ground
of the system.
Clock Input. Data is clocked into the input shift register on the falling edges of CLK IN.
Level-triggered control input (active low). T his is the frame synchronization signal for the input data. When
FSIN
goes low, it enables the input shift register, and data is transferred on the falling edges of CLK IN. If the
address bit is valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling
edge after
FSIN
goes low.
Serial data input. T he device accepts a 16-bit word. T he first bit (DB15) is the DAC MSB, with the remaining
bits following. Next comes the device address bit, A0. If this does not correspond to the logic level on pin A0,
the data is ignored. Finally come the three DAC select bits. T hese determine which DAC in the device is se-
lected for loading.
T his shift register output allows multiple devices to be connected in a daisy chain configuration.
Device address pin. T his input gives the device an address. If DB3 of the serial input stream does not corre-
spond to this, the data which follows is ignored and not loaded to any input latch. However it will appear at
SDOUT irrespective of this.
Asynchronous
LDAC
input. When this input is taken low, all DAC latches are simultaneously updated with the
contents of the input latches.
Asynchronous
CLR
input. When this input is taken low, all DAC latch outputs go to zero.
CLK IN
FSIN
SDIN
SDOUT
A0
LDAC
CLR
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