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參數(shù)資料
| 型號： | AD7564BRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD 5V LP 28SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 500ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電流，單極；8 電流，雙極 |
| 采樣率（每秒）： | 1.8M |
REV.
AD7564
–14–
AD7564 to ADSP-2101/ADSP-2103 Interface
Figure 23 shows a serial interface between the AD7564 and the
ADSP-2101/ADSP-2103 digital signal processors. The ADSP-
2101 operates from 5 V while the ADSP-2103 operates from
3 V supplies. These processors are set up to operate in the
SPORT Transmit Alternate Framing Mode.
The following DSP conditions are recommended: Internal
SCLK; Active low Framing Signal; 16-bit word length. Trans-
mission is initiated by writing a word to the TX register after the
SPORT has been enabled. The data is then clocked out on ev-
ery rising edge of SCLK after TFS goes low. TFS stays low un-
til the next data transfer.
CLR
FSIN
SDIN
CLKIN
LDAC
TFS
DT
SCLK
FO
ADSP-2101/
ADSP-2103
AD7564*
*ADDITIONAL PINS OMMITTED FOR CLARITY
+5V
Figure 23. AD7564 to ADSP-2101/ADSP-2103 Interface
AD7564 to TMS320C25 Interface
Figure 24 shows an interface circuit for the TMS320C25 digital
signal processor. The data on the DX pin is clocked out of
the processor’s Transmit Shift Register by the CLKX signal.
Sixteen-bit transmit format should be chosen by setting the FO
bit in the ST1 register to 0. The transmit operation begins
when data is written into the data transmit register of the
TMS320C25. This data will be transmitted when the FSX line
goes low while CLKX is high or going high. The data, starting
with the MSB, is then shifted out to the DX pin on the rising
edge of CLKX. When all bits have been transmitted, the user
can update the DAC outputs by bringing the XF output flag
low.
CLR
FSIN
SDIN
CLKIN
LDAC
FSX
DX
CLKX
XF
TMS320C25*
AD7564*
*ADDITIONAL PINS OMMITTED FOR CLARITY
+5V
CLOCK
GENERATION
Figure 24. AD7564 to TMS320C25 Interface
APPLICATION HINTS
Output Offset
CMOS D/A converters in circuits such as Figures 17, 18 and 19
exhibit a code dependent output resistance which in turn can
cause a code dependent error voltage at the output of the ampli-
fier. The maximum amplitude of this error, which adds to the
D/A converter nonlinearity, depends on VOS, where VOS is the
amplifier input offset voltage. For the AD7564 to maintain
specified accuracy with VREF at 10 V, it is recommended that
VOS be no greater than 500 V, or (50 × 10
–6)
× (V
REF), over
the temperature range of operation. Suitable amplifiers include
the ADOP-07, ADOP-27, AD711, AD845 or multiple versions
of these.
Temperature Coefficients
The gain temperature coefficient of the AD7564 has a maxi-
mum value of 5 ppm/
°C and a typical value of 2 ppm/°C. This
corresponds to gain shifts of 2 LSBs and 0.8 LSBs respectively
over a 100
°C temperature range. When trim resistors R1 and
R2 are used to adjust full scale in Figures 17 and 18, their tem-
perature coefficients should be taken into account. For further
information see “Gain Error and Gain Temperature Coefficient
of CMOS Multiplying DACs,” Application Note, Publication
Number E630c-5-3/86, available from Analog Devices.
High Frequency Considerations
The output capacitances of the AD7564 DACs work in con-
junction with the amplifier feedback resistance to add a pole to
the open loop response. This can cause ringing or oscillation.
Stability can be restored by adding a phase compensation ca-
pacitor in parallel with the feedback resistor. This is shown as
C1 in Figures 17 and 18.
B
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