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參數(shù)資料
| 型號(hào)： | AD7521LN |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大小： | 0K |
| 描述： | CONV D/A 12BIT 1MHZ 2LSB 18-DIP |
| 標(biāo)準(zhǔn)包裝： | 20 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 20mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 18-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 1M |
6
3. To decrease VOUT, connect a series resistor (0 to 250)
between the reference voltage and the VREF terminal.
4. To increase VOUT, connect a series resistor (0 to 250)
in the IOUT1 amplifier feedback loop.
Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7520 in the
bipolar mode is given in Figure 9. Similar circuits can be
used for AD7521. Using offset binary digital input codes
and positive and negative reference voltage values,
4-Quadrant multiplication can be realized. The “Digital
Input Code/Analog Output Value” table for bipolar mode is
given in Table 2.
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic 0”
input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity
of IOUT2 current and the transconductance amplifier at
IOUT1 output sums the two currents. This configuration
doubles the output range. The difference current resulting
at zero offset binary code, (MSB = “Logic 1”, all other
bits = “Logic 0”), is corrected by using an external resistor,
(10MW), from VREF to IOUT2 .
Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Connect all digital inputs to “Logic 1”.
3. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at
IOUT2 amplifier output.
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to
“Logic 0”.
5. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV
at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1-2-(N-1) volts reading. (N = 8 for
AD7520, and N = 10 for AD7521.).
3. To increase VOUT, connect a series resistor of up to 250
between VOUT and RFEEDBACK.
4. To decrease VOUT, connect a series resister of up to 250
between the reference voltage and the VREF terminal.
TABLE 2. BlPOLAR (OFFSET BINARY) CODE TABLE
DIGITAL INPUT
ANALOG OUTPUT
1111111111
-VREF (1-2-(N-1))
1000000001
-VREF (2-(N-1))
1000000000
0
0111111111
VREF (2-(N-1))
0000000001
VREF (1-2-(N-1))
0000000000
VREF
NOTES:
1. LSB = 2-(N-1) VREF.
2. N = 8 for 7520
N = 10 for 7521.
15
16
1
5
4
13 3
2
AD7520
BIT 1
BIT 10
14
+15V
VREF
IOUT2
6
V
OU
T
-
+
RFEEDBACK
6
-
+
(MSB)
(LSB)
IOUT1
R1 10K
0.01%
R2 10K
0.01%
DIGIT
A
L
INP
U
T
R3
10M
FIGURE 9. BIPOLAR OPERATION (4-QUADRANT
MULTIPLICATION)
AD7520, AD7521
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