參數(shù)資料
型號(hào)： AD7478AARMZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 8BIT 1MSPS 8-MSOP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 8
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 17.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
其它名稱： AD7478AARMZ-REEL7DKR
AD7476A/AD7477A/AD7478A
Rev. F | Page 15 of 28
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7476A/AD7477A/AD7478A are fast, micropower,
12-/10-/8-bit, single-supply analog-to-digital converters (ADCs),
respectively. The parts can be operated from a 2.35 V to 5.25 V
supply. When operated from either a 5 V supply or a 3 V supply,
the AD7476A/AD7477A/AD7478A are capable of throughput
rates of 1 MSPS when provided with a 20 MHz clock. The
AD7476A/AD7477A/AD7478A provide the user with an on-
chip, track-and-hold ADC and a serial interface housed in a
tiny 6-lead SC70 or 8-lead MSOP package, offering the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part but also pro-
vides the clock source for the successive-approximation ADC.
The analog input range is 0 V to VDD. The ADC does not require
an external reference or an on-chip reference. The reference for
the AD7476A/AD7477A/AD7478A is derived from the power
supply and, thus, gives the widest dynamic input range. The
AD7476A/AD7477A/AD7478A also feature a power-down
option to allow power saving between conversions. The power-
down feature is implemented across the standard serial interface,
as described in the Modes of Operation section.
THE CONVERTER OPERATION
AD7476A/AD7477A/AD7478A are successive approximation,
analog-to-digital converters based around a charge redistribu-
tion DAC. Figure 15 and Figure 16 show simplified schematics
of the ADC. Figure 15 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in Position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on VIN.
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
COMPARATOR
SW2
SAMPLING
CAPACITOR
ACQUISITION
PHASE
SW1
A
B
AGND
VDD/2
VIN
02930-015
Figure 15. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 16), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 17 shows the ADC transfer function.
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
COMPARATOR
SW2
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW1
A
B
AGND
VDD/2
VIN
02930-016
Figure 16. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7476A/AD7477A/AD7478A is
straight binary. The designed code transitions occur at the
successive integer LSB values, that is, 1 LSB, 2 LSB, and so on.
The LSB size is VDD/4096 for the AD7476A, VDD/1024 for the
AD7477A, and VDD/256 for the AD7478A. The ideal transfer
characteristic for the AD7476A/AD7477A/AD7478A is shown
000...000
0V
ADC
CODE
ANALOG INPUT
111...111
000...001
000...010
111...110
111...000
011...111
1LSB = VDD/256 (AD7478A)
1LSB
+VDD – 1LSB
1LSB = VDD/1024 (AD7477A)
1LSB = VDD/4096 (AD7476A)
02930-017
Figure 17. AD7476A/AD7477A/AD7478A
Transfer Characteristic
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