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參數(shù)資料
| 型號： | AD7476AYRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 1MSPS LP 8MSOP |
| 設(shè)計資源： | Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165) |
| 標準包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 配用： | EVAL-AD7476ACBZ-ND - BOARD EVALUATION FOR AD7476A |
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AD7476A/AD7477A/AD7478A
Rev. F | Page 17 of 28
Table 8 provides typical performance data with various op amps
used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.
Table 8. AD7476A Typical Performance with Various Input
Buffers, VDD = 3 V
Op Amp in the Input Buffer
AD7476A SNR Performance (dB)
72.3
72.5
71.4
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source imped-
ance depends on the amount of total harmonic distortion (THD)
that can be tolerated. The THD increases as the source impedance
increases, degrading the performance (see Figure 13).
DIGITAL INPUTS
The digital inputs applied to the AD7476A/AD7477A/AD7478A
are not limited by the maximum ratings that limit the analog
input. Instead, the digital inputs applied can reach 7 V and are
not restricted by the VDD + 0.3 V limit as on the analog input.
For example, if operating the AD7476A/AD7477A/AD7478A
with a VDD of 3 V, use 5 V logic levels on the digital inputs.
However, note that the data output on SDATA still has 3 V logic
levels when VDD = 3 V. Another advantage of SCLK and CS not
being restricted by the VDD + 0.3 V limit is that power supply
sequencing issues are avoided. If CS or SCLK are applied before
VDD, there is no risk of latch-up as there would be on the analog
input if a signal greater than 0.3 V were applied prior to VDD.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7476BRT | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| AD7476BRT-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| AD7476BRT-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 600ksps 12-bit Serial 6-Pin SOT-23 T/R |
| AD7476BRTZ-R2 | 功能描述:IC ADC 12BIT 1MSPS SOT23-6 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7476BRTZ-R23 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
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