VDD = 2.35 V to 5" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AD7476ABRM
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 26/29闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ADC 12BIT 2.35V 1MSPS 8-MSOP
瑷�(sh猫)瑷�(j矛)璩囨簮锛� Output Channel Monitoring Using AD5380 (CN0008)
AD5382 Channel Monitor Function (CN0012)
AD5381 Channel Monitor Function (CN0013)
AD5383 Channel Monitor Function (CN0015)
AD5390/91/92 Channel Monitor Function (CN0030)
Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 50
浣嶆暩(sh霉)锛� 12
閲囨ǎ鐜囷紙姣忕锛夛細 1M
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI?
杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 1
鍔熺巼鑰楁暎锛堟渶澶э級锛� 17.5mW
闆诲闆绘簮锛� 鍠浕婧�
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-MSOP
鍖呰锛� 绠′欢
杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� 1 鍊�(g猫)鍠锛屽柈妤�
閰嶇敤锛� EVAL-AD7476ACBZ-ND - BOARD EVALUATION FOR AD7476A
AD7476A/AD7477A/AD7478A
Rev. F | Page 5 of 28
AD7477A SPECIFICATIONS
VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
A Grade2
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 100 kHz sine wave
Signal-to-Noise + Distortion (SINAD)3
61
dB min
Total Harmonic Distortion (THD)3
鈥�72
dB max
Peak Harmonic or Spurious Noise (SFDR)3
鈥�73
dB max
Intermodulation Distortion (IMD)3
Second-Order Terms
鈥�82
dB typ
fa = 100.73 kHz, fb = 90.7 kHz
Third-Order Terms
鈥�82
dB typ
fa = 100.73 kHz, fb = 90.7 kHz
Aperture Delay
10
ns typ
Aperture Jitter
30
ps typ
Full Power Bandwidth
13.5
MHz typ
@ 3 dB
2
MHz typ
@ 0.1 dB
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity
卤0.5
LSB max
Differential Nonlinearity
卤0.5
LSB max
Guaranteed no missed codes to 10 bits
Offset Error3, 4
卤1
LSB max
Gain Error3, 4
卤1
LSB max
Total Unadjusted Error (TUE)3, 4
卤1.2
LSB max
ANALOG INPUT
Input Voltage Range
0 to VDD
V
DC Leakage Current
卤0.5
A max
Input Capacitance
20
pF typ
Track-and-hold in track; 6 pF typ when in hold
LOGIC INPUTS
Input High Voltage, VINH
2.4
V min
1.8
V min
VDD = 2.35 V
Input Low Voltage, VINL
0.8
V max
VDD = 5 V
0.4
V max
VDD = 3 V
Input Current, IIN, SCLK Pin
卤0.5
渭A max
Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
卤10
nA typ
Input Capacitance, CIN5
5
pF max
LOGIC OUTPUTS
Output High Voltage VOH
VDD 鈥� 0.2
V min
ISOURCE = 200 渭A, VDD = 2.35 V to 5.25 V
Output Low Voltage, VOL
0.4
V max
ISINK = 200 渭A
Floating-State Leakage Current
卤1
渭A max
Floating-State Output Capacitance5
5
pF max
Output Coding
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
700
ns max
14 SCLK cycles with SCLK at 20 MHz
Track-and-Hold Acquisition Time3
250
ns max
Throughput Rate
1
MSPS max
鐩搁棞(gu膩n)PDF璩囨枡
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AD7476ABRM-REEL 鍔熻兘鎻忚堪:IC ADC 12BIT 1MSPS 8-MSOP T/R RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊�(g猫)鍠锛屽柈妤�
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AD7476ABRMZ-REEL 鍔熻兘鎻忚堪:IC ADC 12BIT 1MSPS 8-MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊�(g猫)鍠锛屽柈妤�
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