CL 50pF 200 A
參數(shù)資料
型號(hào)： AD7476AAKSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 1MSPS LP SC70-6
設(shè)計(jì)資源： Output Channel Monitoring Using AD5380 (CN0008)
AD5382 Channel Monitor Function (CN0012)
AD5381 Channel Monitor Function (CN0013)
AD5383 Channel Monitor Function (CN0015)
AD5390/91/92 Channel Monitor Function (CN0030)
Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
標(biāo)準(zhǔn)包裝： 10,000
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 17.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 6-TSSOP，SC-88，SOT-363
供應(yīng)商設(shè)備封裝： SC-70-6
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極
配用： EVAL-AD7476ACBZ-ND - BOARD EVALUATION FOR AD7476A
AD7476A/AD7477A/AD7478A
Rev. F | Page 9 of 28
Timing Diagrams
TO OUTPUT
PIN
CL
50pF
200
A
IOH
200
A
IOL
1.6V
02930-002
Figure 2. Load Circuit for Digital Output Timing Specifications
Timing Example 1
Having fSCLK = 20 MHz and a throughput of 1 MSPS, a cycle
time of
t2 + 12.5 (1/fSCLK) + tACQ = 1 s
where:
t2 = 10 ns min, leaving tACQ to be 365 ns. This 365 ns satisfies the
requirement of 250 ns for tACQ.
From Figure 4, tACQ is comprised of
2.5 (1/fSCLK) + t8 + tQUIET
where:
t8 = 36 ns maximum. This allows a value of 204 ns for tQUIET,
satisfying the minimum requirement of 50 ns.
Timing Example 2
Having fSCLK = 5 MHz and a throughput is 315 kSPS yields a
cycle time of
t2 + 12.5 (1/fSCLK) + tACQ = 3.174 s
where:
t2 = 10 ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies
the requirement of 250 ns for tACQ.
From Figure 4, tACQ is comprised of
2.5 (1/fSCLK) + t8 + tQUIET, t8 = 36 ns maximum
This allows a value of 128 ns for tQUIET, satisfying the minimum
requirement of 50 ns.
In this example and with other, slower clock values, the signal
may already be acquired before the conversion is complete, but
it is still necessary to leave 50 ns minimum tQUIET between
conversions. In Example 2, acquire the signal fully at
approximately Point C in Figure 4.
CS
SCLK
SDATA
t2
t6
t3
t4
t7
t5
t8
tCONVERT
tQUIET
ZERO
DB11
DB10
DB2
DB1
DB0
B
THREE-STATE
THREE-
STATE
Z
4 LEADING ZEROS
1
3
13
14
15
16
t1
4
5
2
02930-003
Figure 3. AD7476A Serial Interface Timing Diagram
CS
SCLK
t2
tCONVERT
B
1
2
5
13
14
15
16
C
t8
tQUIET
tACQ
12.5(1/fSCLK)
1/THROUGHPUT
3
4
02930-004
Figure 4. Serial Interface Timing Example
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