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參數(shù)資料
| 型號： | AD7475ARM-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL LP 8-MSOP T/R |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
AD7475/AD7495
Rev. B | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
REF IN
VIN
GND
VDD
VDRIVE
SDATA
SCLK
AD7475
CS
01684-B
-005
Figure 5. AD7475 SOIC/MSOP Pin Configuration
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
REF OUT
VIN
GND
VDD
VDRIVE
SDATA
SCLK
AD7495
CS
01684-B
-006
Figure 6. AD7495 SOIC/MSOP Pin Configuration
Table 5. Pin Descriptions
Pin No.
Mnemonic
Function
1 (AD7475)
REF IN
Reference Input for the AD7475. An external reference must be applied to this input. The voltage range for
the external reference is 2.5 V ± 1% for specified performance. A cap of a least 0.1 μF should be placed on the
REF IN pin.
1 (AD7495)
REF OUT
Reference Output for the AD7495. A minimum 100 nF capacitance is required from this pin to GND. The
internal reference can be taken from this pin, but buffering is required before it is applied elsewhere in a
system.
2
VIN
Analog Input. Single-ended analog input channel. The input range is 0 to REF IN.
3
GND
Analog Ground. Ground reference point for all circuitry on the AD7475/AD7495. All analog input signals and
any external reference signal should be referred to this GND voltage.
4
SCLK
Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the part. This clock input is
also used as the clock source for the AD7475/AD7495 conversion process.
5
SDATA
Data Out, Logic Output. The conversion result from the AD7475/AD7495 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four
leading zeros followed by the 12 bits of conversion data, which is provided MSB first.
6
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage for the serial
interface of the AD7475/AD7495.
7
CS
Chip Select, Active Low Logic Input. This input provides the dual function of initiating conversions on the
AD7475/AD7495 and also frames the serial data transfer.
8
VDD
Power Supply Input. The VDD range for the AD7475/AD7495 is from 2.7 V to 5.25 V.
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