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參數(shù)資料
| 型號： | AD7472YRU-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT PARALLEL 24-TSSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
REV. B
–5–
AD7470/AD7472
Limit at TMIN, TMAX
Parameter
AD7470
AD7472
Unit
Description
fCLK
2
10
kHz min
30
26
MHz max
tCONVERT
436.42
531.66
ns min
tCLK = 1/fCLK IN
tWAKEUP
11
s max
Wake-Up Time
t1
10
ns min
CONVST Pulse Width
t2
CONVST to BUSY Delay,
10
ns max
VDD = 5 V, A and B Versions
15
ns max
VDD = 5 V, Y Version
30
ns max
VDD = 3 V, A and B Versions
35
ns max
VDD = 3 V, Y Version
t3
00
ns max
BUSY to
CS Setup Time
t4
3
00
ns max
CS to RD Setup Time
t5
20
ns min
RD Pulse Width
t6
3
15
ns min
Data Access Time After Falling Edge of
RD
t7
4
88
ns max
Bus Relinquish Time After Rising Edge of
RD
t8
00
ns max
CS to RD Hold Time
t9
Acquisition Time
135
ns max
A and B Versions
140
ns max
Y Version
t10
100
ns min
Quiet Time
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V.
See Figure 1.
2Mark/Space ratio for the CLK inputs is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of
CONVST.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t
7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1 (V
DD = 2.7 V to 5.25 V, REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
200 A
IOL
200 A
IOH
CL
50pF
TO OUTPUT
PIN
1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
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| AD7472YRU-REEL7 | 功能描述:IC ADC 12BIT PARALLEL 24-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7472YRUZ | 制造商:Analog Devices 功能描述:ADC Single SAR 1.5Msps 12-bit Parallel 24-Pin TSSOP |
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