ADDR25–24
參數(shù)資料
型號(hào)： AD7472AR-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/21頁(yè)
文件大小： 0K
描述： IC ADC 12BIT PARALLEL 24-SOIC
標(biāo)準(zhǔn)包裝： 400
位數(shù)： 12
采樣率（每秒）： 1.5M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 12mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
REV. B
AD7470/AD7472
–18–
control line is actually three memory select lines. Internal
ADDR25–24 are decoded into MS3-0; these lines are then asserted
as chip selects. The
DMAR
1 (DMA Request 1) is used in this
setup as the interrupt to signal end of conversion. The rest of
the interface is standard handshaking operation.
AD7470/
AD7472*
ADSP-21065L*
ADDR0–ADDR23
RD
D0–D31
CONVST
RD
BUSY
DB0–DB9
(DB11)
ADDRESS BUS
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
OPTIONAL
DMAR1
ADDRESS
LATCH
ADDRESS
BUS
ADDRESS
DECODER
MSX
CS
Figure 18. Interfacing to ADSP-21065L
AD7470/AD7472 to TMS320C25 Interface
Figure 19 shows an interface between the AD7470/AD7472
and the TMS320C25. The
CONVST signal can be applied
from the TMS320C25 or from an external source. The BUSY
line interrupts the digital signal processor when conversion is
completed. The TMS320C25 does not have a separate
RD
output to drive the AD7470/AD7472
RD input directly. This
has to be generated from the processor
STRB and R/W outputs
with the addition of some glue logic. The
RD signal is OR-gated
with the
MSC signal to provide the WAIT state required in the
read cycle for correct interface timing. The following instruction
is used to read the conversion from the AD7470/AD7472:
IN D,ADC
where D is data memory address and ADC is the AD7470/
AD7472 address. The read operation must not be attempted
during conversion.
ADDRESS
DECODER
AD7470/
AD7472*
TMS320C25*
A0–A15
IS
STRB
R/
W
READY
DMD0–DMD15
CONVST
CS
RD
BUSY
DB0–DB9
(DB11)
ADDRESS BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
OPTIONAL
MSC
DATA BUS
Figure 19. Interfacing to the TMS320C25
AD7470/AD7472 to PIC17C4x Interface
Figure 20 shows a typical parallel interface between the AD7470/
AD7472 and the PIC17C42/43/44. The microcontroller sees
the ADC as another memory device with its own specific
memory address on the memory map. The
CONVST signal can
be controlled by either the microcontroller or an external
source. The BUSY signal provides an interrupt request to the
microcontroller when a conversion ends. The INT pin on the
PIC17C42/43/44 must be configured to be active on the nega-
tive edge. PORTC and PORTD of the microcontroller are
bidirectional and used to address the AD7470/AD7472 and also
to read in the 10-bit (AD7470) or 12-bit (AD7472) data. The
OE pin on the PIC can be used to enable the output buffers on
the AD7470/AD7472 and to perform a read operation.
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS
DECODER
ADDRESS
LATCH
OPTIONAL
PIC17C4x*
AD0–AD15
OE
INT
AD7470/
AD7472*
CONVST
CS
RD
BUSY
DB0–DB9
(DB11)
ALE
Figure 20. Interfacing to the PIC17C4x
AD7470/AD7472 to 80C186 Interface
Figure 21 shows the AD7470/AD7472 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer
can occur between memory and I/O spaces. (The AD7470/
AD7472 occupies one of these I/O spaces.) Each data trans-
fer consumes two bus cycles, one cycle to fetch data and the
other to store data.
After the AD7470/AD7472 has finished conversion, the BUSY
line generates a DMA request to Channel 1 (DRQ1). As a result
of the interrupt, the processor performs a DMA READ opera-
tion which also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request will be serviced before the completion of the next con-
version. This configuration can be used with 6 MHz and 8 MHz
80C186 processors.
80C186*
AD0–AD15
A16–A19
RD
DRQ1
ADDRESS/DATA BUS
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS
LATCH
ADDRESS
BUS
ADDRESS
DECODER
ALE
R
S
Q
AD7470/
AD7472*
CONVST
RD
BUSY
DB0–DB9
(DB11)
OPTIONAL
CS
Figure 21. Interfacing to the 80C186
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