參數(shù)資料
型號(hào)： AD7468BRM
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 8BIT MCRPWR 1.6V 8-MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 8
采樣率（每秒）： 200k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 900µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
AD7466/AD7467/AD7468
Rev. C | Page 20 of 28
POWER CONSUMPTION
The AD7466/AD7467/AD7468 automatically enter power-
down mode at the end of each conversion or if CS is brought
high before the conversion is finished.
When the AD7466/AD7467/AD7468 are in power-down mode,
all the analog circuitry is powered down and the current con-
sumption is typically 8 nA.
To achieve the lowest power dissipation, there are some
considerations the user should keep in mind.
The conversion time is determined by the serial clock
frequency; the faster the SCLK frequency, the shorter the
conversion time. This implies that as the frequency increases,
the part dissipates power for a shorter period of time when the
conversion is taking place, and it remains in power-down mode
for a longer percentage of the cycle time or throughput rate.
Figure 26 shows two AD7466s running with two different
SCLK frequencies, SCLK A and SCLK B, with SCLK A having
the higher SCLK frequency. For the same throughput rate, the
AD7466 using SCLK A has a shorter conversion time than the
AD7466 using SCLK B, and it remains in power-down mode
longer. The current consumption in power-down mode is very
low; thus, the average power consumption is greatly reduced.
This reduced power consumption can be seen in Figure 25,
which shows the supply current vs. SCLK frequency for various
supply voltages at a throughput rate of 100 kSPS. For a fixed
throughput rate, the supply current (average current) drops as
the SCLK frequency increases because the part is in power-
down mode most of the time. It can also be seen that, for a
lower supply voltage, the supply current drops accordingly.
390
S
U
P
L
Y
CURRE
NT
(
μA)
360
330
300
270
240
210
180
150
120
90
60
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
SCLK FREQUENCY (MHz)
fSAMPLE = 100kSPS
TEMP = 25
°C
VDD = 3.6V
VDD = 3.0V
VDD = 2.2V
VDD = 2.7V
VDD = 1.8V
VDD = 1.6V
02643-026
Figure 25. Supply Current vs. SCLK Frequency
for a Fixed Throughput Rate and Different Supply Voltages
SCLK B
SCLK A
116
CONVERSION TIME A
CONVERSION TIME B
1/THROUGHPUT
CS
02643-027
Figure 26. Conversion Time Comparison for Different SCLK Frequencies and a Fixed Throughput Rate
POWER DOWN TIME B
1/THROUGHPUT B
1/THROUGHPUT A
POWER DOWN TIME A
CONVERSION TIME A
CONVERSION TIME B
CS A
SCLK
CS B
116
02643-028
Figure 27. Conversion Time vs. Power-Down Time for a Fixed SCLK Frequency and Different Throughput Rates
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