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參數(shù)資料
| 型號： | AD7468 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1.8伏，微功耗，8/10/12-Bit在ADC的6引腳SOT - 23 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 171K |
| 代理商： | AD7468 |
AD7466/AD7467/AD7468
–12–
REV. PrC
SERIAL INTERFACE
Figure 15, 16, 17 show the detailed timing diagram for
serial interfacing to the AD7466/AD7467/AD7468.The
serial clock provides the conversion clock and also con-
trols the transfer of information from the ADC during a
conversion.
On the
CS falling edge the part begins to power up. The
falling edge of
CS puts the track and hold into track mode
and takes the bus out of tristate.
The conversion is also
initiated at this point and will require 16 SCLK cycles to
complete. On the third SCLK falling edge the part should
be fully powered up, as shown in figure 15 at point B. On
the third SCLK falling edge after the CS falling edge the
track and hold will return to hold. On the 16th SCLK
falling edge the SDATA line will go back into tristate and
the AD7466 will enter power down. If the rising edge of
CS occurs before 16 SCLKs have elapsed then the conver-
sion will be terminated and the SDATA line will go back
into tri-state and the part will enter power down, otherwise
SDATA returns to tri-state on the 16th SCLK falling
edge as shown in Figure 15. Sixteen serial clock cycles
are required to perform the conversion process and to
access data from the AD7466.
For the AD7467, the fourteenth SCLK falling edge will
cause the SDATA line to go back into tri-state and the
part will enter powerdown. If the rising edge of CS occurs
before 14 SCLKs have elapsed then the conversion will be
terminated and the SDATA line will go back into tri-state
and the AD7467 will enter powerdown, otherwise SDATA
returns to tri-state on the 14th SCLK falling edge as
ahown in figure 16. Fourteen serial clock cycles are re-
quired to perform the conversion process and to access
data from the AD7467.
For the AD7468, the 12th SCLK falling edge will cause
the SDATA line to go back into tri-state and the part will
enter powerdown. If the rising edge of CS occurs before
12 SCLKs have elapsed then the conversion will be termi-
nated and the SDATA line will go back into tri-state and
the AD7468 will enter powerdown, otherwise SDATA
returns to tri-state on the 12th SCLK falling edge as
ahown in figure 17. Twelve serial clock cycles are re-
quired to perform the conversion process and to access
data from the AD7468.
CS going low provides the first leading zero to be read in
by the microcontroller or DSP. The remaining data is
then clocked out by subsequent SCLK falling edges be-
ginning with the 2nd leading zero, thus the first falling
clock edge on the serial clock has the first leading zero
provided and also clocks out the second leading zero.
For
the Ad7466 the final bit in the data transfer is valid on the
sixteenth falling edge, having being clocked out on the
previous (15th) falling edge.
Figure 15. AD7466 Serial Interface Timing Diagram
Figure 16. AD7467 Serial Interface Timing Diagram
CS
SCLK
1
5
13
SDATA
4 LEADING ZERO'S
3-STATE
t4
2
34
t3
tquiet
tconvert
t2
3-STATE
DB9
DB8
DB0
t6
t7
t8
14
ZERO
Z
B
t5
CS
tquiet
3-STATE
t5
t8
B
DB0
t7
SCLK
1
SDATA
4 LEADING ZERO'S
ZERO
Z
3-STATE
t4
2
34
t3
tconvert
t2
DB7
t6
8 BITS OF DATA
12
11
Figure 17. AD7468 Serial Interface Timing Diagram
CS
SCLK
1
5
13
15
SDATA
4 LEADING ZERO'S
3-STATE
t4
2
34
16
t5
t3
tquie
t
tconvert
t2
3-STATE
DB11
DB10
DB2
DB0
t6
t7
t8
14
ZERO
Z
B
DB1
pecifications
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