VDD 1 SCLK 2 SDATA 3 CS 4
參數(shù)資料
型號: AD7452BRTZ-R2
廠商: Analog Devices Inc
文件頁數(shù): 28/29頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 555KSPS SOT23-8
標準包裝: 1
位數(shù): 12
采樣率(每秒): 555k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 7.25mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標準包裝
輸入數(shù)目和類型: 1 個差分,雙極
產(chǎn)品目錄頁面: 777 (CN2011-ZH PDF)
其它名稱: AD7452BRTZ-R2DKR
AD7452
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1
SCLK
2
SDATA
3
CS
4
VREF
VIN+
VIN–
GND
8
7
6
5
03154-A-004
AD7452
TOP VIEW
(Not to Scale)
Figure 4. 8-Lead SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Mnemonic
Function
VREF
Reference Input for the AD7452. An external reference must be applied to this input. For a 5 V power supply, the reference is
2.5 V (± 1%) for specified performance. For a 3 V power supply, the reference is 2 V (± 1%) for specified performance. This pin
should be decoupled to GND with a capacitor of at least 0.1 F. See the Reference section for more details.
VIN+
Positive Terminal for Differential Analog Input.
VIN–
Negative Terminal for Differential Analog Input.
GND
Analog Ground. Ground reference point for all circuitry on the AD7452. All analog input signals and any external reference
signal should be referred to this GND voltage.
CS
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7452 and
framing the serial data transfer.
SDATA
Serial Data. Logic output. The conversion result from the AD7452 is provided on this output as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of
conversion data, which are provided MSB first. The output coding is twos complement.
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process.
VDD
Power Supply Input. VDD is 3 V (+20%/–10%) or 5 V (± 5%). This supply should be decoupled to GND with a 0.1 F capacitor
and a 10 F tantalum capacitor in parallel.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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