- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1981 > AD7450ABRT-R2 (Analog Devices Inc)IC ADC 12BIT W/DIFF INP SOT-23-8 PDF資料下載
參數(shù)資料
| 型號： | AD7450ABRT-R2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT W/DIFF INP SOT-23-8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 剪切帶 (CT) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
| 配用： | EVAL-AD7450CBZ-ND - BOARD EVALUATION FOR AD7450 |
| 其它名稱： | AD7450ABRT-R2CT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
AD7440/AD7450A
Rev. C | Page 24 of 28
If CS is brought high before the 10th falling edge of SCLK, the
AD7440/AD7450A again goes back into power-down. This
avoids accidental power-up due to glitches on the CS line or an
inadvertent burst of eight SCLK cycles while CS is low. So
although the device may begin to power up on the falling edge
of CS, it again powers down on the rising edge of CS as long as
it occurs before the 10th SCLK falling edge.
POWER-UP TIME
The power-up time of the AD7440/AD7450A is typically 1 μs,
which means that with any frequency of SCLK up to 18 MHz,
one dummy cycle is always sufficient to allow the device to
power up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, tQUIET, must still be allowed from the point at which the
bus goes back into three-state after the dummy conversion to
the next falling edge of CS.
When running at the maximum throughput rate of 1 MSPS, the
AD7440/AD7450A power up and acquire a signal within
±0.5 LSB in one dummy cycle, 1 μs. When powering up from
the power-down mode with a dummy cycle, as in Figure 43, the
track-and-hold, which was in hold mode while the part was
powered down, returns to track mode after the first SCLK edge
the part receives after the falling edge of CS. This is shown as
Point A in Figure 43.
Although at any SCLK frequency one dummy cycle is sufficient
to power up the device and acquire VIN, it does not mean that a
full dummy cycle of 16 SCLKs must always elapse to power up
the device and acquire VIN fully; 1 μs is sufficient to power up
the device and acquire the input signal.
For example, if a 5 MHz SCLK frequency was applied to the
ADC, the cycle time would be 3.2 μs (1/(5 MHz) × 16). In one
dummy cycle, 3.2 μs, the part would be powered up and VIN
acquired fully. However, after 1 μs with a 5 MHz SCLK, only
five SCLK cycles would have elapsed. At this stage, the ADC
would be fully powered up and the signal acquired. So in this
case, the CS can be brought high after the 10th SCLK falling
edge and brought low again after a time, tQUIET, to initiate the
conversion.
When power supplies are first applied to the device, the ADC
may power up in either power-down mode or normal mode.
Because of this, it is best to allow a dummy cycle to elapse to
ensure the part is fully powered up before attempting a valid
conversion. Likewise, if the user wants the part to power up in
power-down mode, the dummy cycle may be used to ensure the
device is in power-down by executing a cycle such as the one
shown in Figure 42.
Once supplies are applied to the AD7440/AD7450A, the power-
up time is the same as that when powering up from power-
down mode. It takes about 1 μs to power up fully if the part
powers up in normal mode. It is not necessary to wait 1 μs
before executing a dummy cycle to ensure the desired mode of
operation. Instead, the dummy cycle can occur directly after
power is supplied to the ADC. If the first valid conversion is
then performed directly after the dummy conversion, ensure
that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the power-down
mode, the part returns to track mode upon the first SCLK edge
applied after the falling edge of CS. However, when the ADC
powers up initially after supplies are applied, the track-and-hold
is already in track mode. Assuming the user has the facility to
monitor the ADC supply current, this means the ADC powers
up in the desired mode of operation, and thus a dummy cycle is
not required to change mode. A dummy cycle is therefore not
required to place the track-and-hold into track mode.
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7440/AD7450A
when not converting, the average power consumption of the
ADC decreases at lower throughput rates. Figure 44 shows how,
as the throughput rate is reduced, the device remains in its
power-down state longer and the average power consumption is
reduced accordingly for both 5 V and 3 V power supplies.
For example, if the AD7440/AD7450A are operated in
continuous sampling mode with a throughput rate of 100 kSPS
and an SCLK of 18 MHz, and the device is placed in power-
down mode between conversions, the power consumption is
calculated as follows:
Power Dissipation during Normal Operation = 9.25 mW max
(for VDD = 5 V)
If the power-up time is one dummy cycle (1 μs), and the
remaining conversion time is another cycle (1 μs), the
AD7440/AD7450A can be said to dissipate 9.25 mW for 2 μs1
during each conversion cycle.
If the throughput rate = 100 kSPS, the cycle time = 10 μs and
the average power dissipated during each cycle is
(2/10) × 9.25 mW = 1.85 mW.
For the same scenario, if VDD = 3 V, the power dissipation
during normal operation is 4 mW max.
The AD7440/AD7450A can now be said to dissipate 4 mW for
2 μs1 during each conversion cycle.
1This figure assumes a very short time to enter power-down mode. This
increases as the burst of clocks used to enter this mode is increased.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7450BRMZ | IC ADC 12BIT DIFF IN 1MSPS 8MSOP |
| AD7451BRMZ | IC ADC 12BIT DIFF 1MSPS 8MSOP |
| AD7452BRT-R2 | IC ADC 12BIT 555KSPS SOT23-8 |
| AD7453BRTZ-REEL7 | IC ADC 12BIT W/DIFF INP SOT23-8 |
| AD7457BRTZ-REEL7 | IC ADC 12BIT PSEUDO-DIFF SOT23-8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7450ABRT-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, 1 MSPS 10-Bit and 12-Bit ADCs in an 8-Lead SOT-23 |
| AD7450ABRTZ-REEL7 | 功能描述:IC ADC 12BIT DIFF 1MSPS SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7450ABRTZ-REEL72 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, 1 MSPS ADCs in an 8-Lead SOT-23 |
| AD7450AR | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 8-Pin SOIC N 制造商:Rochester Electronics LLC 功能描述:3V/5V DIFFERENTIAL INPUT 12 BIT SAR IC - Bulk |
| AD7450ARM | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 8-Pin MSOP 制造商:Rochester Electronics LLC 功能描述:3V/5V DIFFERENTIAL INPUT 12 BIT SAR IC - Bulk 制造商:Analog Devices 功能描述:IC 12BIT SAR ADC SMD 7450 MSOP8 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。