- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗5789 > AD744JR (Analog Devices Inc)IC OPAMP BIFET 13MHZ PREC 8SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD744JR |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/12闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC OPAMP BIFET 13MHZ PREC 8SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 98 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | J-FET |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 75 V/µs |
| -3db甯跺锛� | 13MHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 30pA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 300µV |
| 闆绘祦 - 闆绘簮锛� | 3.5mA |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 25mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | ±4.5 V ~ 18 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 绠′欢 |
REV.C
鈥�2鈥�
AD744鈥揝PECIFICATIONS (@ +25 C and 15 V dc, unless otherwise noted)
AD744J/A/S
AD744K/B/T
Model
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
INPUT OFFSET VOLTAGE
1
Initial Offset
0.3
1.0
0.25
0.5
mV
Offset
TMIN to TMAX
2
1.0
mV
vs. Temp.
5
20
5
10
V/掳C
vs. Supply
2
82
95
88
100
dB
vs. Supply
TMIN to TMAX
82
88
dB
Long-Term Stability
15
V/month
INPUT BIAS CURRENT
3
Either Input
VCM = 0 V
30
100
30
100
pA
Either Input @ TMAX =VCM = 0 V
J, K
70
掳C
0.7
2.3
0.7
2.3
nA
A, B, C
85
掳C
1.9
6.4
1.9
6.4
nA
S, T
125
掳C
31
102
31
102
nA
Either Input
VCM = +10 V
40
150
40
150
pA
Offset Current
VCM = 0 V
20
50
10
50
pA
Offset Current @ TMAX =VCM = 0 V
J, K
70
掳C
0.4
1.1
0.2
1.1
nA
A, B, C
85
掳C
1.3
3.2
0.6
3.2
nA
S, T
125
掳C20
52
10
52
nA
FREQUENCY RESPONSE
Gain BW, Small Signal
G = 鈥�1
8
13
9
13
MHz
Full Power Response
VO = 20 V p-p
1.2
MHz
Slew Rate, Unity Gain
G = 鈥�1
45
75
50
75
V/
s
Settling Time to 0.01%
4
G = 鈥�1
0.5
0.75
0.5
0.75
s
Total Harmonic
f = 1 kHz
Distortion
R1
鈮� 2 k
VO = 3 V rms
0.0003
%
INPUT IMPEDANCE
Differential
3
10
12
||5.5
3
10
12
||5.5
||pF
Common Mode
3
10
12
||5.5
3
10
12
||5.5
||pF
INPUT VOLTAGE RANGE
Differential
5
卤 20
V
Common-Mode Voltage
+14.5, 鈥�11.5
V
Over Max Operating Range
6
鈥�11
+13
鈥�11
+13
V
Common-Mode
Rejection Ratio
VCM =
卤10 V
78
88
82
88
dB
TMIN to TMAX
76
84
80
84
dB
VCM =
卤11 V
72
84
78
84
dB
TMIN to TMAX
70
80
74
80
dB
INPUT VOLTAGE NOISE
0.1 to 10 Hz
2
V p-p
f = 10 Hz
45
nV/
鈭欻z
f = 100 Hz
22
nV/
鈭欻z
f = 1 kHz
18
nV/
鈭欻z
f = 10 kHz
16
nV/
鈭欻z
INPUT CURRENT NOISE
f = 1 kHz
0.01
pA/
鈭欻z
OPEN LOOP GAIN
7
VO =
卤10 V
RLOAD
鈮� 2 k
200
400
250
400
V/mV
TMIN to TMAX
100
V/mV
OUTPUT CHARACTERISTICS
Voltage
RLOAD
鈮� 2 k
+13, 鈥�12.5
+13.9, 鈥�13.3
+13, 鈥�12.5
+13.9, 鈥�13.3
V
TMIN to TMAX
卤 12
+13.8, 鈥�13.1
卤 12
+13.8, 鈥�13.1
V
Current
Short Circuit
25
mA
Capacitive Load
8
Gain = 鈥�1
1000
pF
POWER SUPPLY
Rated Performance
卤 15
V
Operating Range
卤 4.5
卤 18
卤 4.5
卤 18
V
Quiescent Current
3.5
5.0
3.5
4.0
mA
NOTES
1Input offset voltage specifications are guaranteed after 5 minutes of operation at T
A = +25
掳C.
2PSRR test conditions: +V
S = 15 V, 鈥揤S = 鈥�12 V to 鈥�18 V and +VS = +12 V to +18 V, 鈥揤S = 鈥�15 V.
3Bias Current Specifications are guaranteed maximum at either input after 5 minutes of operation at T
A = +25
掳C. For higher temperature, the current doubles every 10掳C.
4Gain = 鈥�1, R
L = 2 k, CL = 10 pF, refer to Figure 25.
5Defined as voltage between inputs, such that neither exceeds
卤10 V from ground.
6Typically exceeding 鈥�14.1 V negative common-mode voltage on either input results in an output phase reversal.
7Open-Loop Gain is specified with V
OS both nulled and unnulled.
8Capacitive load drive specified for C
COMP = 20 pF with the device connected as shown in Figure 32. Under these conditions, slew rate = 14 V/
s and 0.01% settling time = 1.5 s typical.
Refer to Table II for optimum compensation while driving a capacitive load.
Specifications subject to change without notice. All min and max specifications are guaranteed.
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| AD744JR-REEL7 | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:OP Amp Single GP 卤18V 8-Pin SOIC N T/R 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:PRECISION BIPOLAR OP AMP - Tape and Reel |
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