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參數(shù)資料
| 型號： | AD74111YRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO MONO LP 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 77 / 89 |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 85 / 93 |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-AD74111EBZ-ND - BOARD EVAL FOR AD74111 |
REV. 0
–16–
AD74111
Table VII. Control Register B
Third MCLK
Second MCLK
First MCLK
R/W
ADDRESS
RES
Reserved
Divider
15
14, 13, 12, 11
10
9, 8, 7, 6
5, 4
3, 2
1, 0
1
0001
0
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
10 = Divide by 3
11 = Divide by 1
Table VIII. Control Register C
DAC and ADC
Low Group
DAC
ADC High-
R/W
ADDRESS
RES
Reserved
Word Width
Delay
De-emphasis
Pass Filter
15
14, 13, 12, 11
10
9, 8, 7, 6
5, 4
3
2, 1
0
1
0010
0
00 = 16 Bits
0 = Disabled
00 = None
0 = Disabled
01 = 20 Bits
1 = Enabled
01 = 44.1 kHz
1 = Enabled
10 = 24 Bits
10 = 32 kHz
11 = 24 Bits
11 = 48 kHz
Table IX. Control Register D
Master/
R/W
ADDRESS
RES
Multiframe Sync
Reserved
DM/MM
DSP Mode
Fast DCLK
Slave
15
14, 13, 12, 11
10
9
8, 7, 6, 5, 4
3
2
1
0
1
0011
0
0 = Normal Mode
0
0 = Data Mode
0 = 16 Bits
0 = 128
fS
0 = Slave
1 = MFS Mode
1 = Mixed Mode 1 = 32 Bits
1 = 256
fS
1 = Master
Table VI. Control Register A
ADC Input
Reference
R/W
ADDRESS
RES
Reserved
Amplifier
ADC
DAC
Reference
Amplifier
Reserved
15
14, 13, 12, 11
10
9, 8, 7
6
5
4
3
2
1, 0
1
0000
0
0 = Off
0
1 = On
Function
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