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參數資料
| 型號： | AD7357YRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 20/21頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL14BIT 4.2MSPS 16TSSOP |
| 設計資源： | DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061) |
| 標準包裝： | 1 |
| 位數： | 14 |
| 采樣率（每秒）： | 4.2M |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 59mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸入數目和類型： | 2 個差分，雙極 |
| 產品目錄頁面： | 777 (CN2011-ZH PDF) |
AD7357
Rev. B | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
VINA–
REFA
REFGND
VINB–
REFB
AGND
VINA+
VINB+
16
15
14
13
12
11
10
9
SCLK
SDATAA
SDATAB
CS
VDD
AGND
DGND
VDRIVE
AD7357
TOP VIEW
(Not to Scale)
07
75
7-
0
02
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2
VINA+, VINA
Analog Inputs of ADC A. These analog inputs form a fully differential pair.
3, 6
REFA, REFB
Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the
REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each
reference pin with a 10 μF capacitor. Provided that the output is buffered, the on-chip reference can be taken
from these pins and applied externally to the rest of the system. The nominal internal reference voltage is
2.048 V and appears at these pins. These pins can also be overdriven by an external reference. The input
voltage range for the external reference is 2.048 V + 100 mV to VDD.
4
REFGND
Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Any external
reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between
this pin and the REFA and REFB pins.
5, 11
AGND
Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. All analog input
signals should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
7, 8
VINB, VINB+
Analog Inputs of ADC B. These analog inputs form a fully differential pair.
9
VDD
Power Supply Input. The VDD range for the AD7357 is 2.5 V ± 10%. The supply should be decoupled to AGND
with a 0.1 μF capacitor and a 10 μF tantalum capacitor.
10
CS
Chip Select. Active low, logic input. This input provides the dual function of initiating conversions on the
AD7357 and framing the serial data transfer.
12
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
13, 14
SDATAB, SDATAA
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the
AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of
both ADCs. The data stream consists of two leading zeros, followed by the 14 bits of conversion data. The data
is provided MSB first. If CS is held low for 18 SCLK cycles rather than 16, then two trailing zeros appear after the
14 bits of data. If CS is held low for an additional 18 SCLK cycles on either SDATA or SDATAB , the data from the
other ADC follows on the SDATA pins. This allows data from a simultaneous conversion on both ADCs to be
gathered in serial format on either SDATA or SDATAB.
A
15
SCLK
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This
clock is also used as the clock source for the conversion process.
16
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD.
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