參數(shù)資料
型號: AD7328BRUZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 33/37頁
文件大?。?/td> 0K
描述: IC ADC 12BIT+ SAR 8CHAN 20TSSOP
設計資源: Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047)
標準包裝: 1,000
系列: iCMOS®
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 30mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,單極;4 個差分,雙極
AD7328
Data Sheet
Rev. C | Page 4 of 36
B Version
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
Differential Nonlinearity2
0.9/+1.5
LSB
Differential mode; guaranteed no missing codes to
13 bits
±0.9
LSB
Single-ended mode; guaranteed no missing codes to
12 bits
0.7/+1
LSB
Single-ended/pseudo differential mode (LSB = FSR/8192)
Offset Error2, 5
4/+9
LSB
Single-ended/pseudo differential mode
7/+10
LSB
Differential mode
Offset Error Match2, 5
±0.6
LSB
Single-ended/pseudo differential mode
±0.5
LSB
Differential mode
Gain Error2, 5
±8
LSB
Single-ended/pseudo differential mode
±14
LSB
Differential mode
Gain Error Match2, 5
±0.5
LSB
Single-ended/pseudo differential mode
±0.5
LSB
Differential mode
Positive Full-Scale Error2, 6
±4
LSB
Single-ended/pseudo differential mode
±7
LSB
Differential mode
Positive Full-Scale Error Match2, 6
±0.5
LSB
Single-ended/pseudo differential mode
±0.5
LSB
Differential mode
Bipolar Zero Code Error2, 6
±8.5
LSB
Single-ended/pseudo differential mode
±7.5
LSB
Differential mode
Bipolar Zero Code Error Match2, 6
±0.5
LSB
Single-ended/pseudo differential mode
±0.5
LSB
Differential mode
Negative Full-Scale Error2, 6
±4
LSB
Single-ended/pseudo differential mode
±6
LSB
Differential mode
Negative Full-Scale Error Match2,6
±0.5
LSB
Single-ended/pseudo differential mode
±0.5
LSB
Differential mode
ANALOG INPUT
Input Voltage Ranges
Reference = 2.5 V; see Table 6
(Programmed via Range Register)
±10
V
VDD = 10 V min, VSS = 10 V min, VCC = 2.7 V to 5.25 V
±5
V
VDD = 5 V min, VSS = 5 V min, VCC = 2.7 V to 5.25 V
±2.5
V
VDD = 5 V min, VSS = 5 V min, VCC = 2.7 V to 5.25 V
0 to 10
V
VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V
Pseudo Differential VIN()
Input Range
VDD = 16.5 V, VSS = 16.5 V, VCC = 5 V; see Figure 40 and
±3.5
V
Reference = 2.5 V; range = ±10 V
±6
V
Reference = 2.5 V; range = ±5 V
±5
V
Reference = 2.5 V; range = ±2.5 V
+3/5
V
Reference = 2.5 V; range = 0 V to +10 V
DC Leakage Current
±200
nA
VIN = VDD or VSS
Input Capacitance3
13.5
pF
When in track, ±10 V range
16.5
pF
When in track, ±5 V and 0 V to +10 V ranges
21.5
pF
When in track, ±2.5 V range
3
pF
When in hold, all ranges
REFERENCE INPUT/OUTPUT
Input Voltage Range
2.5
3
V
Input DC Leakage Current
±1
A
Input Capacitance
10
pF
Reference Output Voltage
2.5
V
Long Term Stability
150
ppm
For 1000 hours
Output Voltage Hysteresis
50
ppm
Reference Output Voltage Error
at 25°C
±5
mV
Reference Output Voltage
TMIN to TMAX
±10
mV
Reference Temperature Coefficient
25
ppm/°C
6
ppm/°C
Reference Output Impedance
7
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