VOUT (mV)
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD7305BRU
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 2/20闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DAC 8BIT QUAD R-R 20-TSSOP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Data Converter Fundamentals
DAC Architectures
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 75
瑷�(sh猫)缃檪闁擄細 1µs
浣嶆暩(sh霉)锛� 8
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 骞惰伅(li谩n)
杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 4
闆诲闆绘簮锛� 闆� ±
鍔熺巼鑰楁暎锛堟渶澶э級锛� 60mW
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 20-TSSOP锛�0.173"锛�4.40mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-TSSOP
鍖呰锛� 绠′欢
杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� 4 闆诲锛屽柈妤�锛�4 闆诲锛岄洐妤�
閲囨ǎ鐜囷紙姣忕锛夛細 1M
AD7304/AD7305
Rev. C | Page 10 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT (mV)
144
120
0
015
REFERENCE INPUT VOLTAGE (V)
1.0
0.6
鈥�1.0
鈥�5.0
5.0
鈥�3.0
INL
(
L
SB)
鈥�1.0
1.0
3.0
0.2
鈥�0.2
鈥�0.6
VDD = +5V
VSS = 鈥�5V
DATA = 0x80
TA = +25掳C
DAC A
DAC B
DAC C
DAC D
01114-013
3
I OUT
S
INK
CURRE
NT
(mA)
69
12
96
72
48
24
VDD = +5V
VSS = 鈥�5V
VREF = VDD
DATA = 0x00
01114-010
Figure 10. IOUT Sink vs. VOUT Rail-to-Rail Performance
VOUT OUTPUT VOLTAGE (V)
鈥�35
鈥�28
0
4.0
5.0
4.2
I OUT
S
O
URCE
CURRE
NT
(mA)
4.4
4.6
4.8
鈥�21
鈥�14
鈥�7
VDD = +5V
VSS = 鈥�5V
VREF = VDD
DATA = 0xFF
01114-011
Figure 11. IOUT SOURCE vs. VOUT Rail-to-Rail Performance
CODE (Decimal)
+1
0
256
32
INL
(
L
SB)
64
96
128
160
192
224
0
+1
鈥�1
+1
鈥�1
+1
鈥�1
0
鈥�1
DAC A
DAC B
DAC C
DAC D
VDD = +5V
VSS = 鈥�5V
VREF = +2.5V
TA = +25掳C
01114-012
Figure 12. INL vs. Code, All DAC Channels
Figure 13. INL vs. Reference Input Voltage
CODE (Decimal)
0.500
鈥�0.500
0
256
32
DNL
(LS
B
)
64
96
128
160
192
224
0.375
0
鈥�0.125
鈥�0.250
鈥�0.375
0.250
0.125
VDD = +5V
VSS = 鈥�5V
VREF = +2.5V
01114-014
Figure 14. DNL vs. Code
TEMPERATURE (
掳C)
4.0
3.6
2.0
鈥�55
125
鈥�35
ZER
O
-S
C
A
L
E
VOLTA
GE
(
m
V)
鈥�15
5
25
45
65
85
105
3.2
2.8
2.4
VDD = 5.5V
VSS = 0V
VREF = 5.45V
01114-015
Figure 15. Zero-Scale Voltage vs. Temperature
鐩搁棞(gu膩n)PDF璩囨枡
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