參數(shù)資料
型號: AD7303BRZ
廠商: Analog Devices Inc
文件頁數(shù): 7/16頁
文件大?。?/td> 0K
描述: IC DAC 8BIT DUAL R-R 8-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準包裝: 98
設(shè)置時間: 1.2µs
位數(shù): 8
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 6.93mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): 833k
產(chǎn)品目錄頁面: 784 (CN2011-ZH PDF)
AD7303
–15–
REV. 0
LDAA
#$18
0, 0, 0, 1, 1, 0, 0, 0
*
SCLK and DIN enabled as outputs
LDAA
#$53
STAA
SPCR
SPI on, Master mode, CPOL=0, CPHA=0, Clock rate =E/32
*
BSR
UPDATE
Update AD7303 output.
JMP
#$E000
Restart.
*
UPDATE
PSHX
Save relevant registers.
PSHY
PSHA
*
LDAA
#$00
Control Word "0, 0, 0, 0, 0, 0, 0, 0"
STAA
DIN 1
Load both DAC A and DAC B DAC registers from shift register
with internal reference selected.
LDAA
#$AA
Data Word "1, 0, 1, 0, 1, 0, 1, 0"
STAA
DIN 2
*
LDX
#DIN1
Stack pointer at first first byte to send via DIN 1.
LDY
#$1000
Stack pointer at on chip registers.
*
BCLR
PORTC,Y $80
Assert SYNC.
TRANSFER
LDAA
0,X
Get BYTE to transfer via SPI.
STAA
SPDR
Write to DIN register to start transfer.
*
WAIT
LDAA
SPSR
Wait for SPIF to be set to indicate that transfer has been completed.
BPL
WAIT
SPIF is the MSB of the SPCR. SPIF is automatically reset if in a set
state when the status register is read.
*
INX
Increment counter for transfer of second byte.
CPX
#DIN 2+1
16 bits transferred?
BNE
TRANSFER
If not, transfer second BYTE.
*Execute instruction
BSET
PORTC,Y $80
Bring SYNC back high.
PULA
Restore registers.
PULY
PULX
RTS
Return to main program.
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