power up until after the falling edge" />
參數(shù)資料
型號(hào)： AD7274BRM
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 3MSPS HS LP 8MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 12
采樣率（每秒）： 3M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 18mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極
AD7273/AD7274
Rev. 0 | Page 18 of 28
edge of CS, the device begins to power up and continues to
power up until after the falling edge of the 10th SCLK as long as
CS is held low. The power-up time required must elapse before
a conversion can be initiated, as shown in Figure 33. See the
Power-Up Times section for the power-up times associated with
the AD7273/AD7274.
POWER-UP TIMES
The AD7273/AD7274 has two power-down modes, partial
power-down and full power-down, which are described in
detail in the Modes of Operation section. This section deals
with the power-up time required when coming out of either of
these modes.
To power up from partial power-down mode, one cycle is
required. Therefore, with a SCLK frequency of up to 48 MHz,
one dummy cycle is sufficient to allow the device to power up
from partial power-down mode. Once the dummy cycle is
complete, the ADC is fully powered up and the input signal is
acquired properly. The quiet time, tQUIET, must be allowed from
the point where the bus goes back into three-state after the
dummy conversion to the next falling edge of CS.
To power up from full power-down, approximately 1 μs should
be allowed from the falling edge of CS, shown in Figure 33 as
tPOWER-UP. Note that during power-up from partial power-down
mode, the track-and-hold, which is in hold mode while the part
is powered down, returns to track mode after the first SCLK
edge is received after the falling edge of CS. This is shown as
Point A in Figure 31.
When power supplies are first applied to the AD7273/AD7274,
the ADC can power up in either of the power-down modes or
in normal mode. Because of this, it is best to allow a dummy
cycle to elapse to ensure that the part is fully powered up before
attempting a valid conversion. Likewise, if the part is to be kept
in partial power-down mode immediately after the supplies are
applied, two dummy cycles must be initiated. The first dummy
cycle must hold CS low until after the 10th SCLK falling edge
(see Figure 29). In the second cycle, CS must be brought high
between the second and 10th SCLK falling edges (see Figure 30).
Alternatively, if the part is to be placed into full power-down
mode after the supplies are applied, three dummy cycles must
be initiated. The first dummy cycle must hold CS low until after
the 10th SCLK falling edge (see Figure 29); the second and third
dummy cycles place the part into full power-down mode (see
Figure 32). See also the Modes of Operation section.
CS
SCLK
110
12
14
16
AD7273/AD7674
SDATA
VALID DATA
04973-029
Figure 29. Normal Mode Operation
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