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參數(shù)資料
型號： AD7273BRMZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 29/29頁
文件大?。?/td> 0K
描述： IC ADC 10BIT 3MSPS HS LP 8MSOP
標(biāo)準(zhǔn)包裝： 3,000
位數(shù)： 10
采樣率（每秒）： 3M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 18mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個單端，單極
AD7273/AD7274
Rev. 0 | Page 8 of 28
TIMING EXAMPLES
For the AD7274, if CS is brought high during the 14
th SCLK
rising edge after the two leading zeros and 12 bits of the
conversion are provided, the part can achieve the fastest
throughput rate, 3 MSPS. If CS is brought high during the 16
th
SCLK rising edge after the two leading zeros, 12 bits of the
conversion, and two trailing zeros are provided, a throughput
rate of 2.97 MSPS is achievable. This is illustrated in the
following two timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz, and
the throughput is 3 MSPS. This produces a cycle time of
t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns min and
tACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ.
Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t9 + tQUIET,
where t9 = 4.2 ns max. This allows a value of 52.8 ns for tQUIET,
satisfying the minimum requirement of 4 ns.
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time
of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and
tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) +
t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum
requirement of 4 ns for tQUIET.
12
3
4
5
13
14
15
16
SCLK
SDATA
THREE-STATE
THREE-
STATE TWO LEADING
ZEROS
TWO TRAILING
ZEROS
B
CS
t3
tCONVERT
t2
ZERO
Z
DB11
DB10
DB9
DB1
DB0
ZERO
t6
t5
t8
t1
tQUIET
1/THROUGHPUT
t4
t7
04973-005
Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle
12
3
4
5
13
14
SCLK
SDATA
THREE-STATE
THREE-
STATE
TWO LEADING
ZEROS
B
CS
t3
tCONVERT
t2
ZERO
Z
DB11
DB10
DB9
DB1
DB0
t6
t9
t1
tQUIET
1/THROUGHPUT
t4
t7
04973-006
t5
Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle
12
3
4
5
13
12
14
15
16
SCLK
B
CS
tCONVERT
t2
t8
t1
tQUIET
1/THROUGHPUT
12.5(1/fSCLK)
tACQUISITION
04973-007
Figure 7. Serial Interface Timing 16 SCLK Cycle
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參數(shù)描述
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