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參數(shù)資料
| 型號(hào)： | AD7249BRZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | LC2MOS Dual 12-Bit Serial DACPORT |
| 中文描述： | DUAL, SERIAL INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大小： | 149K |
| 代理商： | AD7249BRZ |
REV. C
–6–
AD7249
Internal Reference
The AD7249 has an on-chip temperature compensated buried
Zener reference which is factory trimmed to 5 V
± 50 mV. The
reference voltage is provided at the REFOUT pin. This refer-
ence can be used to provide the reference voltage for the D/A
converter by connecting the REFOUT pin to the REFIN pin.
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500
A to an
external load. The maximum recommended capacitance on
REFOUT for normal operation is 50 pF. If the reference output
is required to drive a capacitive load greater than 50 pF, then a
200
resistor should be placed in series with the capacitive
load. Figure 3 shows the suggested REF OUT decoupling
scheme, a 200
resistor and the parallel combination of a
10
F tantalum and a 0.1 F ceramic capacitor. This decoupling
scheme reduces the noise spectral density of the reference.
REFOUT
200
10 F
0.1 F
EXT LOAD
Figure 3. Reference Decoupling Scheme
External Reference
In some applications, the user may require a system reference or
some other external reference to drive the AD7249. References
such as the AD586 provide an ideal external reference source
(See Figure 10). The REFIN voltage is internally buffered by a
unity gain amplifier before being applied to the D/A converter.
The D/A converter is scaled for a 5 V reference and the device is
tested with 5 V applied to REFIN. Other reference voltages may
be used with degraded performance. Figure 4 shows the degra-
dation in linearity vs. REFIN.
REFIN – Volts
1.0
2
LINEARITY
ERROR
–
LSBs
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3
4567
8
9
VDD = +15V
VSS = –15V
TA = +25 C
INL
DNL
Figure 4. Linearity vs. REFIN Voltage
Op Amp Section
The output of the voltage-mode D/A converter is buffered by a
noninverting CMOS amplifier. The ROFS input allows three
output voltage ranges to be selected. The buffer amplifier is
capable of developing +10 V across a 2 k
load to AGND.
The output amplifier can be operated from a single +15 V sup-
ply by tying VSS = 0 V.
The amplifier can also be operated from dual supplies to allow
an additional bipolar output range of –5 V to +5 V. Dual sup-
plies are necessary for the bipolar output range but can also be
used for the unipolar ranges to give faster settling time to volt-
ages near 0 V, to allow full sink capability of 2.5 mA over the
entire output range and to eliminate the effects of negative offsets
on the transfer characteristic (outlined previously). A plot of the
output sink capability of the amplifier is shown in Figure 5.
OUTPUT VOLTAGE – Volts
3
0
I SINK
–
mA
2
1
0
2
468
10
VSS = 0V
VSS = –15V
Figure 5. Amplifier Sink Current
FREQUENCY – Hz
500
50
nV/
Hz
100
200
500
1k
2k
5k
10k
VDD = +15V
VSS = 0V
TA = +25 C
200
100
50
20
0
REFERENCE DECOUPLING COMPONENTS ARE
A 200
RESISTOR IN SERIES WITH A PARALLEL
COMBINATION OF 10 F AND 0.1 F TO GND.
*
20k
50k
100k
REFERENCE
(NO DECOUPLING)
REFERENCE
(DECOUPLED*)
OUTPUT WITH ALL
0s ON DAC
Figure 6. Noise Spectral Density vs. Frequency
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