- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗1980 > AD7249BR (Analog Devices Inc)IC DAC 12BIT SRL W/REF 16-SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD7249BR |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/14闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DAC 12BIT SRL W/REF 16-SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Data Converter Fundamentals DAC Architectures |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | DACPORT® |
| 瑷�(sh猫)缃檪闁擄細 | 10µs |
| 浣嶆暩(sh霉)锛� | 12 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 2 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 300mW |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC W |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 2 闆诲锛屽柈妤�锛�2 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 125k |
AD7249
鈥�3鈥�
Limit at TMIN to TMAX
Parameter
(All Versions)
Unit
Conditions/Comments
t1
4
200
ns min
SCLK Cycle Time
t2
15
ns min
SYNC to SCLK Falling Edge Setup Time
t3
50
ns min
SYNC to SCLK Hold Time
t4
0
ns min
Data Setup Time
t5
150
ns min
Data Hold Time
t6
0
ns min
SYNC High to LDAC Low
t7
20
ns min
LDAC Pulsewidth
t8
0
ns min
LDAC High to SYNC Low
t9
50
ns min
CLR Pulsewidth
t10
20
ns min
SYNC High Time
NOTES
1Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage
level of 1.6 V.
2See Figure 8.
3Power supply tolerance, A Version:
卤 10%; B, S Versions: 卤 5%.
4SCLK Mark/Space Ratio range is 45/55 to 55/45.
(VDD = +12 V to +15 V,
3 V
SS = 0 V or 鈥�12 V to 鈥�15 V,
3 AGND = DGND = 0 V, R
L = 2 k
,
CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
1
(TA = +25
掳C unless otherwise noted)
VDD to AGND, DGND . . . . . . . . . . . . . . . . . . 鈥�0.3 V to +17 V
VSS to AGND, DGND . . . . . . . . . . . . . . . . . . +0.3 V to 鈥�17 V
AGND to DGND . . . . . . . . . . . . . . . . . 鈥�0.3 V to VDD + 0.3 V
VOUTA, B
2 to AGND . . . . . . . . . . . . V
SS 鈥� 0.3 V to VDD + 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD
REFIN to AGND . . . . . . . . . . . . . . . . . 鈥�0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . 鈥�0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . . 鈥�40
掳C to +85掳C
Extended (S Version) . . . . . . . . . . . . . . . . . 鈥�55
掳C to +125掳C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150
掳C
Storage Temperature Range . . . . . . . . . . . . . 鈥�65
掳C to +150掳C
Power Dissipation Plastic DIP . . . . . . . . . . . . . . . . . . . 600 mW
胃JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . +117掳C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300
掳C
Power Dissipation, Cerdip . . . . . . . . . . . . . . . . . . . . . . 600 mW
胃JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76掳C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300
掳C
Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . 600 mW
胃JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75掳C/W
Lead Temperature (Soldering)
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215
掳C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220
掳C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.
2The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7249 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
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