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參數(shù)資料
| 型號： | AD7194BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/57頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SPI 4.8KHZ 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個差分，單極；8 個差分，雙極；16 個偽差分，單極；16 偽差分，雙極 |
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AD7194
Data Sheet
Rev. A | Page 38 of 56
An internal zero-scale calibration, system zero-scale calibration,
and system full-scale calibration can be performed at any
output data rate. An internal full-scale calibration can be
performed at any output data rate for which the filter word,
FS[9:0], is divisible by 16, FS[9:0] being the decimal equivalent
of the 10-bit word written to Bit FS9 to Bit FS0 in the mode
register. Therefore, internal full-scale calibrations can be
performed at output data rates such as 10 Hz or 50 Hz when
chop is disabled. Using these lower output data rates results in
better calibration accuracy.
The offset error is, typically, ±150 μV/gain. If the gain is changed, it
is advisable to perform a calibration. A zero-scale calibration (an
internal zero-scale calibration or a system zero-scale calibration)
reduces the offset error to the order of the noise.
The gain error of the AD7194 is factory calibrated at a gain of 1
with a 5 V power supply at ambient temperature. Following this
calibration, the gain error is ±0.001%, typically, at 5 V. Table 27
shows the typical uncalibrated gain error for the different gain
settings.
Table 27. Typical Precalibration Gain Error vs. Gain
Gain
Precalibration Gain Error (%)
8
0.11
16
0.20
32
0.23
64
0.29
128
0.4
An internal full-scale calibration reduces the gain error to
±0.001%, typically, when the gain is equal to 1. For higher gains,
the gain error post internal full-scale calibration is ±0.003%,
typically when AVDD is equal to or higher than 4.75 V. When
AVDD is less than 4.75 V, the gain error post internal full-scale
calibration is ±0.005%, typically.
When AVDD is less than 4.75 V, the CLK_DIV bit must be set
when performing internal full-scale calibrations. This increases
the calibration time by a factor of 2. The accuracy of the internal
full-scale calibration is further increased if chop is enabled and
a low output data rate is used while performing the calibration.
A system full-scale calibration reduces the gain error to the
order of the noise irrespective of the analog power supply
voltage.
The AD7194 gives the user access to the on-chip calibration
registers, allowing the microprocessor to read the calibration
coefficients of the device and also to write its own calibration
coefficients from prestored values in the EEPROM. A read of
the registers can be performed at any time. However, the ADC
must be placed in power-down or idle mode when writing to
the registers. The values in the calibration registers are 24 bits
wide. The span and offset of the part can also be manipulated
using the registers.
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| AD7194BCPZ-REEL7 | 功能描述:IC ADC 24BIT SPI 4.8KHZ 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation |
| AD7195BCPZ | 功能描述:IC AFE 24BIT 4.8K 32LFSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7195BCPZ | 制造商:Analog Devices 功能描述:IC ADC 24BIT 4.8KSPS CSP-32 |
| AD7195BCPZ-RL | 功能描述:IC AFE 24BIT 4.8K 32LFSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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