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參數(shù)資料
| 型號(hào)： | AD7153BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CDC 12BIT 1/2CH 10MSOP |
| 特色產(chǎn)品： | AD715x Series Capacitance-to-Digital Converters & Evaluation Board |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 電容數(shù)字轉(zhuǎn)換器 |
| 分辨率（位）： | 12 b |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 單電源 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
AD7152/AD7153
Rev. 0 | Page 4 of 24
Parameter
Min
Typ
Max
Unit1
Test Conditions/Comments
POWER REQUIREMENTS
VDD-to-GND Voltage
2.7
3.6
V
VDD = 3.3 V, nominal
Current, IDD9
100
120
μA
Current Power-Down Mode, IDD9
1
5
μA
Temperature ≤ 25°C
3
10
μA
Temperature = 85°C
1 Capacitance units: 1 pF = 1012 F; 1 fF = 1015 F; 1 aF = 1018 F.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Except Channel 2 in differential mode. To achieve the specified performance in differential mode, the I2C interface must be idle during the capacitance conversion to
prevent signal coupling from the SCL pin to the adjacent CIN2() pin.
4 Factory calibrated. The absolute error includes factory gain calibration error and integral nonlinearity error all at 25°C. At different temperatures, compensation for
gain drift over temperature is required.
5 Specification is not production tested but guaranteed by design.
6 A system offset calibration is effectively a conversion; therefore, the offset error is of the order of the conversion noise. This applies after calibration at the temperature,
capacitive input range, and applied VDD of interest. The capacitive input offset can be reduced using a system offset calibration. Large offsets should be removed using
CAPDACs.
7 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.
8 The CAPDAC resolution is five bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can
further reduce the CIN offset or the unchanging CIN component.
9 Digital inputs equal to VDD or GND.
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