GND 1 VDD
參數(shù)資料
型號(hào): AD7151BRMZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 25/28頁(yè)
文件大?。?/td> 0K
描述: IC CAP CONV 1CH ULT LP 10MSOP
特色產(chǎn)品: AD715x Series Capacitance-to-Digital Converters & Evaluation Board
標(biāo)準(zhǔn)包裝: 50
類型: 電容數(shù)字轉(zhuǎn)換器
輸入類型: 電壓
輸出類型: 數(shù)字
接口: 2 線串口
電流 - 電源: 120µA
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 781 (CN2011-ZH PDF)
AD7151
Rev. 0 | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1
VDD 2
NC 3
CIN 4
NC
NC = NO CONNECT
5
SDA
10
SCL
9
NC
8
OUT
7
EXC
6
AD7151
TOP VIEW
(Not to Scale)
07
08
6-
0
03
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
GND
Ground Pin.
2
VDD
Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, for example,
0.1 μF X7R multilayer ceramic.
3
NC
This pin should be left as an open circuit or connected to GND.
4
CIN
CDC Capacitive Input. The measured capacitance (sensor) is connected between the EXC pin and the CIN pin.
5
NC
This pin should be left as an open circuit.
6
EXC
CDC Excitation Output. The measured capacitance is connected between the EXC pin and the CIN pin.
7
OUT
Logic Output. High level on this output indicates proximity detected on the capacitive input.
8
NC
This pin should be left as an open circuit.
9
SCL
Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if not provided
elsewhere in the system.
10
SDA
Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided
elsewhere in the system.
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