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參數(shù)資料
| 型號： | AD7147WPACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CAP-TO-DGTL CONV PROG 24LFCSP |
| 標準包裝： | 5,000 |
| 系列： | CapTouch™ |
| 類型： | 電容數(shù)字轉換器 |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 電壓電源： | 單電源 |
| 電源電壓： | 2.6 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
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AD7147
Data Sheet
Rev. D | Page 34 of 72
SERIAL INTERFACE
The AD7147 is available with an SPI-compatible interface. The
AD7147-1 is available with an I2C-compatible interface. Both
parts are the same, with the exception of the serial interface.
SPI INTERFACE
The AD7147 has a 4-wire serial peripheral interface (SPI). The
SPI has a data input pin (SDI) for inputting data to the device, a
data output pin (SDO) for reading data back from the device,
and a data clock pin (SCLK) for clocking data into and out of
the device. A chip select pin (CS) enables or disables the serial
interface. CS is required for correct operation of the SPI. Data is
clocked out of the AD7147 on the negative edge of SCLK and
data is clocked into the device on the positive edge of SCLK.
SPI Command Word
All data transactions on the SPI bus begin with the master
taking CS from high to low and sending out the command
word. This indicates to the AD7147 whether the transaction is a
read or a write and provides the address of the register from
which to begin the data transfer. The following bit map shows
the SPI command word.
MSB
LSB
15
14
13
12
11
10
9:0
1
0
R/W
Register address
Bits[15:11] of the command word must be set to 11100 to
successfully begin a bus transaction.
Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates
a write.
Bits[9:0] contain the target register address. When reading or
writing to more than one register, this address indicates the
address of the first register to be written to or read from.
Writing Data
Data is written to the AD7147 in 16-bit words. The first word
written to the device is the command word, with the read/write
bit set to 0. The master then supplies the 16-bit input data-word
on the SDI line. The AD7147 clocks the data into the register
addressed in the command word. If there is more than one
word of data to be clocked in, the AD7147 automatically incre-
ments the address pointer and clocks the subsequent data-word
into the next register.
The AD7147 continues to clock in data on the SDI line until
either the master finishes the write transition by pulling CS high
or the address pointer reaches its maximum value. The AD7147
address pointer does not wrap around. When it reaches its
maximum value, any data provided by the master on the SDI
line is ignored by the AD7147.
CW
11
CW
10
CW
13
CW
12
SDI
CW
15
CW
14
CW
9
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
D2
D1
D0
CW
8
t1
t4
16-BIT DATA
5
32
6
7
8
9
10
11
12
13
14
15
16
30
31
t8
t5
SCLK
12
3
4
D15
D14
D13
17
18
19
CS
ENABLE WORD
R/W
REGISTER ADDRESS
t2
t3
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR THE CONTROL WORD AND 16 BITS FOR THE DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 0 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
16-BIT COMMAND WORD
06663-
046
Figure 49. Single Register Write SPI Timing
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