參數(shù)資料
型號(hào)： AD7142ACPZ-1500RL7
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 32/73頁(yè)
文件大?。?/td> 0K
描述： IC CAP-TO-DGTL CONV PROG 32LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 電容數(shù)字轉(zhuǎn)換器
分辨率（位）： 16 b
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 2.6 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： AD7142ACPZ-1500RL7DKR
AD7142
Rev. A | Page 37 of 72
POWER-UP SEQUENCE
When the AD7142 is powered up, the following sequence is
recommended when initially developing the AD7142 and μP
serial interface:
1.
Turn on the power supplies to the AD7142.
2.
Write to the Bank 2 registers at Address 0x080 through
Address 0x0DF. These registers are contiguous so a
sequential register write sequence can be applied.
Note: The Bank 2 register values are unique for each
application. Register values are provided by Analog
Devices after the sensor board has been developed.
3.
Write to the Bank 1 registers at Address 0x000 through
Address 0x007 as follows. These registers are contiguous so
a sequential register write sequence can be applied (see
Caution: At this time, Address 0x001 must remain set to
default value 0x0000 during this contiguous write
operation.
Register values:
Address 0x000 = 0x00B2
Address 0x001 = 0x0000
Address 0x002 = 0x3230
Address 0x003 = 0x14C8
Address 0x004 = 0x0832
Address 0x005 = 0x0000
Address 0x006 = 0x0000
Address 0x007 = 0x0001 (The AD7142 interrupt is asserted
approximately every 36 ms.)
4.
Write to the Bank 1 register, Address 0x001 = 0x0FFF.
5.
Read back the corresponding interrupt status register at
Address 0x008, Address 0x009, or Address 0x00A. This is
determined by the interrupt output configuration as
explained in the Interrupt Output section.
Note: The specific registers required to be read back
depend on each application. Analog Devices provides this
information after the sensor board has been developed.
6.
Repeat Step 5 every time INT is asserted.
05702-
0
40
FIRST CONVERSION SEQUENCE
CONVERSION
STAGE
0
CONVERSION STAGES DISABLED
1
2
34
5
6
78
9
10 11
0
12
910 11
0
1
2
910 11
0
1
SECOND CONVERSION
SEQUENCE
THIRD CONVERSION
SEQUENCE
Figure 56. Recommended Start-Up Sequence
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