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參數(shù)資料
| 型號： | AD713JNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP BIFET QUAD PREC 14DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 4 |
| 轉(zhuǎn)換速率： | 20 V/µs |
| -3db帶寬： | 4MHz |
| 電流 - 輸入偏壓： | 55pA |
| 電壓 - 輸入偏移： | 300µV |
| 電流 - 電源： | 10mA |
| 電流 - 輸出 / 通道： | 25mA |
| 電壓 - 電源，單路/雙路(±)： | 9 V ~ 36 V，±4.5 V ~ 18 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 766 (CN2011-ZH PDF) |
AD713
Rev. F | Page 13 of 20
loop gain. At high frequencies, where the loop gain is low, the
amplifier output impedance can approach its open-loop value.
STS
1
(MSB) DB11
HIGH
BITS
MIDDLE
BITS
LOW
BITS
(LSB) DB0
2
DB10
3
DB9
4
28
27
AO
26
25
DB8
5
DB7
6
DB6
7
CE
24
REF OUT
23
AC
22
DB5
8
REF IN
21
DB4
9
VEE
20
DB3
10
BIP OFF
19
DB2
11
10VIN
18
DB1
12
VLOGIC
17
13
VCC
16
DC
14 20VIN
15
AD574A
TOP VIEW
(Not to Scale)
12/8
CS
R/C
GAIN ADJUST
±10V
ANALOG
INPUT
R2 100
R1 100
OFFSET ADJUST
ANALOG COM
00
82
4-
03
9
1/4
AD713
+15V
0.1F
4
–15V
0.1F
11
Figure 37. AD713 as an ADC Buffer
Most IC amplifiers exhibit a minimum open-loop output imped-
ance of 25 Ω, due to current limiting resistors. A few hundred
microamps reflected from the change in converter loading can
introduce errors in instantaneous input voltage. If the analog-
to-digital conversion speed is not excessive and the bandwidth
of the amplifier is sufficient, the amplifier output returns to
the nominal value before the converter makes its comparison.
However, many amplifiers have relatively narrow bandwidths,
yielding slow recovery from output transients. The AD713 is
ideally suited as a driver for ADCs because it offers both a wide
bandwidth and a high open-loop gain.
008
24-
0
40
100
90
10
0%
1mV
AD713 BUFF
200ns
500mV
10V ADC IN
Figure 38. Buffer Recovery Time Source Current = 2 mA
008
24-
0
41
100
90
10
0%
1mV
AD713 BUFF
200ns
500mV
–5V ADC IN
Figure 39. Buffer Recovery Time Sink Current = 1 mA
Driving A Large Capacitive Load
The circuit of Figure 40 uses a 100 Ω isolation resistor that
enables the amplifier to drive capacitive loads exceeding
1500 pF; the resistor effectively isolates the high frequency
feedback from the load and stabilizes the circuit. Low frequency
feedback is returned to the amplifier summing junction via the
low-pass filter formed by the 100 Ω series resistor and the load
this connection.
+VS
–VS
1/4
AD713
4
11
0.1F
30pF
4.99k
CL RL
100
0.1F
OUTPUT
INPUT
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
RL
2k
10k
20k
CL UP TO
1500pF
1000pF
00
82
4-
04
2
Figure 40. Circuit for Driving a Large Capacitance Load
008
24-
0
43
100
90
10
0%
5V
1s
Figure 41. Transient Response, RL = 2 kΩ, CL = 500 pF
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