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參數(shù)資料
| 型號： | AD698APZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LVDT SIGNAL COND 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 信號調(diào)節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | LVDT |
| 電流 - 電源： | 15mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 791 (CN2011-ZH PDF) |
AD698
REV. B
–9–
FREQUENCY – Hz
0
100k
100
1k
10k
10
0
–30
–60
–70
0
–10
–20
–50
–40
–360
–60
–240
–300
–420
–180
–120
GAIN
–
dB
PHASE
SHIFT
–
Degrees
0.1F
0.033F
0.01F
R2 = 81k
fEXC = 10kHz
0.1F
0.033F
0.01F
R2 = 81k
fEXC = 10kHz
Figure 15. Gain and Phase Characteristics vs. Frequency
(0 kHz–50 kHz)
FREQUENCY – Hz
0
100
1k
10k
10
0
–30
–60
–70
–10
–20
–50
–40
0
–360
–60
–240
–300
–180
–120
GAIN
–
dB
PHASE
SHIFT
–
Degrees
0.1F
0.033F
0.01F
R2 = 81k
fEXC = 10kHz
0.1F
0.033F
0.01F
R2 = 81k
fEXC = 10kHz
Figure 16. Gain and Phase Characteristics vs. Frequency
(0 kHz–10 kHz)
Figure 16 shows a more limited frequency range with enhanced
accuracy. The figures are transfer functions with the input to be
considered as a sinusoidally varying mechanical position and the
output as the voltage from the AD698; the units of the transfer
function are volts per inch. The value of C2, C3, and C4, from
Figure 7, are all equal and designated as a parameter in the fig-
ures. The response is approximately that of two real poles.
However, there is appreciable excess phase at higher frequen-
cies. An additional pole of filtering can be introduced with a
shunt capacitor across R2, Figure 7; this will also increase phase
lag.
When selecting values of C2, C3 and C4 to set the bandwidth of
the system, a trade-off is involved. There is ripple on the “dc”
position output voltage, and the magnitude is determined by the
filter capacitors. Generally, smaller capacitors will give higher
system bandwidth and larger ripple. Figures 17 and 18 show the
magnitude of ripple as a function of C2, C3 and C4, again all
equal in value. Note also a shunt capacitor across R2, Figure 7,
is shown as a parameter. The value of R2 used was 81 k
with a
Schaevitz E100 LVDT.
C2, C3, C4; C2 = C3 = C4 –
F
RIPPLE
–
mV
rms
1k
100
0.1
0.01
0.1
10
1
10
1
2.5kHz, C
SHUNT
1nF
2.5kHz, C
SHUNT
10nF
Figure 17. Output Voltage Ripple vs. Filter Capacitance
C2, C3, C4; C2 = C3 = C4 –
F
RIPPLE
–
mV
rms
1k
100
0.1
0.001
0.01
10
0.1
10
1
10kHz, C
SHUNT
1nF
10kHz, C
SHUNT
10nF
1
Figure 18. Output Voltage Ripple vs. Filter Capacitance
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| AD698APZ | 制造商:Analog Devices 功能描述:IC LVDT SIGNAL COND 28PLCC 制造商:Analog Devices 功能描述:IC, LVDT SIGNAL COND, 28PLCC |
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