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參數資料
| 型號： | AD679JNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 128KSPS 28-DIP |
| 標準包裝： | 1 |
| 位數： | 14 |
| 采樣率（每秒）： | 128k |
| 數據接口： | 并聯 |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 745mW |
| 電壓電源： | 模擬和數字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 供應商設備封裝： | 28-PDIP |
| 包裝： | 管件 |
| 輸入數目和類型： | 1 個單端，單極；1 個單端，雙極 |
| 產品目錄頁面： | 777 (CN2011-ZH PDF) |
AD679
REV. D
–4–
Parameter
Symbol
Min
Max
Unit
SC Delay
tSC
50
ns
Conversion Time
tC
6.3
s
Conversion Rate
1
tCR
7.8
s
Convert Pulse Width
tCP
0.097
3.0
s
Aperture Delay
tAD
520
ns
Status Delay
tSD
0
400
ns
Access Time
2, 3
tBA
10
100
ns
10
57
4
ns
Float Delay
5
tFD
10
80
ns
Output Delay
tOD
0ns
Format Setup
tFS
100
ns
OE Delay
tOE
20
ns
Read Pulse Width
tRP
195
ns
Conversion Delay
tCD
400
ns
EOCEN Delay
tEO
50
ns
NOTES
1Includes acquisition time.
2Measured from the falling edge of
OE/EOCEN (0.8 V) to the time at which the
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.
3C
OUT = 100 pF.
4C
OUT = 50 pF.
5Measured from the rising edge of
OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5. See Figure 4; C
OUT
= 10 pF.
Specifications subject to change without notice.
(All device types TMIN to TMAX, VCC = +12 V
5%, VEE = –12 V
5%, VDD = +5 V
10%)
NOTES
1IN ASYNCHRONOUS MODE, STATE OF
CS DOES NOT AFFECT OPERATION.
SEE THE START CONVERSION TRUTH TABLE FOR DETAILS.
2
EOCEN = LOW (SEE FIGURE 3). IN SYNCHRONOUS MODE, EOC IS A THREE-
STATE OUTPUT. IN ASYNCHRONOUS MODE, EOC IS AN OPEN DRAIN OUTPUT.
3DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
Figure 1. Conversion Timing
Figure 2. Output Timing
NOTE
1EOC IS A THREE-STATE OUTPUT IN SYNCHRONOUS MODE
AND AN OPEN DRAIN OUTPUT IN ASYNCHRONOUS. ACCESS (tBA)
AND FLOAT (tFD) TIMING SPECIFICATIONS DO NOT APPLY IN
ASYNCHRONOUS MODE WHERE THEY ARE A FUNCTION OF THE
TIME CONSTANT FORMED BY THE 10pF OUTPUT CAPACITANCE
AND THE PULL-UP RESISTOR.
Figure 3. EOC Timing
TEST
VCP
COUT
ACCESS TIME HIGH Z TO LOGIC LOW 5V
100pF
FLOAT TIME LOGIC HIGH TO HIGH Z
0V
10pF
ACCESS TIME HIGH Z TO LOGIC HIGH
0V
100pF
FLOAT TIME LOGIC LOW TO HIGH Z
5V
10pF
IOL
IOH
DOUT
VCP
COUT
Figure 4. Load Circuit for Bus Timing Specifications
TIMING SPECIFICATIONS
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