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參數(shù)資料
| 型號： | AD679BD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SAMPLING 28-CDIP |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 128k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 745mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-CDIP（0.605"，15.37mm） |
| 供應(yīng)商設(shè)備封裝： | 28-CDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
AD679
REV. D
–9–
CONVERSION CONTROL
In synchronous mode (SYNC = HIGH), both chip select (
CS)
and start convert (
SC) must be brought LOW to start a conver-
sion.
CS should be LOW t
SC before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started by
bringing
SC low, regardless of the state of CS.
Before a conversion is started, end-of-convert (EOC) is HIGH
and the sample-and-hold is in track mode. After a conversion is
started, the sample-and-hold goes into hold mode and EOC
goes LOW, signifying that a conversion is in progress. During
the conversion, the sample-and-hold will go back into track
mode and start acquiring the next sample.
In track mode, the sample-and-hold will settle to
0.003%
(14 bits) in 1.5
s maximum. The acquisition time does not
affect the throughput rate as the AD679 goes back into track
mode more than 2
s before the next conversion. In multichan-
nel systems, the input channel can be switched as soon as EOC
goes LOW.
Bringing
OE LOW t
OE after CS goes LOW makes the output
register contents available on the output data bits (DB7–DB0).
A period of time, tCD, is required after OE is brought HIGH
before the next SC instruction is issued.
If
SC is held LOW, conversion accuracy may deteriorate. For
this reason,
SC should not be held low in an attempt to operate
in a continuously converting mode.
Table I. Start Conversion Truth Table
Inputs
SYNC
CS
SC
Status
Synchronous
1
X
No Conversion
Mode
1
0
f
Start Conversion
1
f
0
Start Conversion
(Not Recommended)
10
0Continuous Conversion
(Not Recommended)
Asynchronous
0
X
1
No Conversion
Mode
0
X
f
Start Conversion
0X
0Continuous Conversion
(Not Recommended)
1= HIGH voltage level.
0= LOW voltage level.
X= Don’t care.
f = HIGH to LOW transition. Must stay low for t = tCP.
Table II. 14-Bit Mode Coding Format (1 LSB = 0.61 mV)
Unipolar Coding
Bipolar Coding
(Straight Binary)
(Twos Complement)
VIN*
Output Code
VIN* (V)
Output Code
0.00000 V
000 . . . 0
–5.00000
100 . . . 0
5.00000 V
100 . . . 0
–0.00061
111 . . . 1
9.99939 V
111 . . . 1
0.00000
000 . . . 0
+2.50000
010 . . . 0
+4.99939
011 . . . 1
*Code center.
END-OF-CONVERT
In asynchronous mode, end-of-convert (EOC) is an open-drain
output (requiring a minimum 3 k
pull-up resistor) enabled by
end-of-convert enable (
EOCEN). In synchronous mode, EOC
is a three-state output that is enabled by
EOCEN and CS. See
Table III. Access (tBA) and float (tFD) timing specifications do
not apply in asynchronous mode where they are a function of
the time constant formed by the external load capacitance and
the pull-up resistor.
OUTPUT ENABLE OPERATION
The data bits (DB7–DB0) are three-state outputs that are enabled
by chip select (
CS) and output enable (OE). CS should be
LOW tOE before OE is brought LOW.
When EOC goes HIGH, the conversion is completed and the
output data may be read. The output is read in two steps as a
16-bit word, with the high byte read first, followed by the low
byte. High byte enable (
HBE) controls the output sequence.
The 14-bit result is left justified within the 16-bit field.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFOUT),
output coding is twos complement binary.
POWER-UP
The AD679 typically requires 10
s after power-up to reset
internal logic.
Table III. Conversion Status Truth Table
Inputs
Output
SYNC
CS EOCEN EOC
Status
Synchronous
1
0
Converting
Mode
1
0
1
Not Converting
11
XHigh Z
Either
1X
1High Z
Either
Asynchronous
0X
00
Converting
Mode
*
0X
0High Z
Not Converting
0X
1High Z
Either
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
*EOC requires a pull-up resistor in asynchronous mode.
Table IV. Output Enable Truth Table
Inputs
Outputs
HBE
(
CS U OE)
DB7 . . . DB0
X1
← High Z →
Unipolar or
0
a b c d e f g h
Bipolar
1
0
i j
k l m n 0 0
1= HIGH voltage level.
a = MSB.
0= LOW voltage level.
n = LSB.
X= Don’t care.
U = Logical OR.
Data coding is binary for unipolar mode and twos complement binary for
bipolar mode.
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